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  1. floating_point_multiplier_verilog

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  2. This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:935
    • 提供者:sajad
  1. frac_divider_verilog

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  2. This code has written in verilog and it can divide two fraction numbers in fixed point standard .In this code ni shows the number of bits of inputs and no shows the number of bits of output and if we want more precision we can change this parameters
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:681
    • 提供者:sajad
  1. -Elliptic

    0下载:
  2. We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coproc
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:117173
    • 提供者:陳曉慧
  1. Source

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  2. I2C 控制器的 Verilog源程序以及I2C规范说明-The I2C bus provides a simple two-wire means of communication. This protocol is used in many applications.SDRAM modules implement a serial EEPROM that supports the I2C protocol. This is used so that a micro
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:9241
    • 提供者:zx
  1. CLK_DIV

    0下载:
  2. verilog HDL写的时钟通用计数分频程序,设置系统时钟,并根据目标时钟,设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the targ
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:745
    • 提供者:fightsea
  1. ThBird

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  2. 雷鸟车尾灯设计,采用VERILOG语言开发,大家可以逐渐熟悉状态机实验。-Thunderbird car taillight design, using VERILOG language, everyone can become familiar with the state machine experiment.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:405568
    • 提供者:仲崇鑫
  1. dds1

    0下载:
  2. 用ALTERA 公司的fpga芯片,编程语言是VerilogHDL,实现DDS数字信号发生器,可以产生正弦信号,三角信号,矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1577200
    • 提供者:郭晨
  1. lcd_top

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  2. 针对xilinx fpga开发用verilog写的lcd接口驱动,下载到板子上可以点亮LCD灯-Xilinx fpga for development verilog write with the LCD interface drive, downloaded to the board can light LCD lamp
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:3468
    • 提供者:张康
  1. ps_top

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  2. verilog写ps2接口驱动程序,对状态机的描述。把键盘串行的13为数据转换为并行的8为数据,并储存在寄存器-The needle verilog write ps2 interface drivers, to the descr iption of the state machine. The keyboard for data transfer of serial and parallel for the 8 for data, and stored in a register to xi
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:3683
    • 提供者:张康
  1. led

    0下载:
  2. 该程序是用Verilog编写的关于led的硬件电路描述程序,运用该程序可以对其进行仿真及测试。-The program is written in Verilog hardware circuit descr iption of the procedures led the use of the program can be simulated and tested.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:16341
    • 提供者:周狩猎
  1. calender

    1下载:
  2. 这是用Verilog语言编写的万年历源代码,其中以小时为最小单位,可以区分闰年。有瑕疵还望海涵。-This is the calendar source code written in Verilog language, which hour is the smallest unit that can differentiate between leap years.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-22
    • 文件大小:25816
    • 提供者:年伦
  1. vga_rtl

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  2. VGA显示FPGA verilog代码.分辨率可设置。-VGA display verilog code for FPGA.resolution can be set
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:2970
    • 提供者:wuzhen
  1. EP3C

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  2. 利用Verilog编写的串口收发程序,波特率可调,经测试完全可以应用。-Use of serial transceiver in Verilog program, the baud rate is adjustable, can be applied by the test completely.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-06
    • 文件大小:1411952
    • 提供者:lobee
  1. compare

    0下载:
  2. 比较器,四位的比较器,verilog的语言编写的,可以用-The comparator, the comparator four, Verilog language, can be used
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-23
    • 文件大小:244760
    • 提供者:hx
  1. poc

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  2. verilog 写的POC接口代码。测试波形功能通过。内有波形模拟CPU以及仿真文件。-A poc module written by verilogHDL.Can be used in communicating with MCUs. The simulate wave file is already inside.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:219681
    • 提供者:王润
  1. lcd

    0下载:
  2. FPGA控制12864液晶显示,本程序已经调试通过,可以根据自己的要求随意变换显示内容。本程序用Verilog编写。-FPGA to control the 12,864 LCD, debugging has passed, can transform reality according to their Chinese characters, written in Verilog program
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:246387
    • 提供者:子莫言
  1. mul1617

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  2. 采用verilog RTL级语言,实现了有符号的16位乘17位的乘法器。特点是:采用流水的结构,可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真,并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Thr
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:1168
    • 提供者:李小白
  1. lcd1602_test

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  2. 1602verilog 驱动好使,已运行通过,修改管脚后可直接使用-verilog Drive Drive so that has been run by the modified pin can be used directly
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:472738
    • 提供者:朱颜
  1. 16QAM

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  2. 详细介绍了16QAM的fpga实现过程,并通过verilog语言编程,可以得到比较好的效果-Details the the the 16QAM fpga implementation process, and can get better results through the verilog language programming,
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-19
    • 文件大小:5389820
    • 提供者:焦栋
  1. led_0_7

    0下载:
  2. 与键盘扫描功能相对应,实现7段数码管的显示功能,在单片机中有较大用处。verilog-fullfill the function of displaying in verilog language. You can use it combined with keyboard scanning
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:683
    • 提供者:王源
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