搜索资源列表
EchoClear
- vc++源码，消除回声处理， 可用于音频处理； -vc++ source code, deal with the elimination of echo can be used for audio processing
key1
- 用verilog硬件描述语言写的一个LED的程序，可以用到各种模块中，实用性很强，欢迎大家下载使用。-Verilog hardware descr iption language used to write procedures for a LED can be used in a variety of modules are very practical, and welcome to download.
GPIO
- GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
lai_PWM
- FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
svc_timer33ms
- Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) co
i2c_slv_ctrl
- I2c总线 verilog实现，可用于quartus设计-Verilog bus I2c realized, can be used to design quartus
timeclock
- 基于verilog的时钟定时器的硬件实现，可以实现时钟定时报时功能-Based on the verilog hardware timer clock can be achieved from time to time time clock function
c54x_verilog
- TI 的TMS320C54X的DSP的芯片软核verilog源代码，可以帮助初学者深入了解该系列DSP片内资源核结构，值得参考！-TMS320C54X of TI' s DSP chip soft-core verilog source code, can help beginners a better picture of the family of DSP-chip resources, nuclear structure, it is also useful!
canbus
- verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
iic
- 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
UART_VHDL_Verilog
- UART的Verilog_源码,适合初学者学习can协议。-UART s Verilog source, suitable for beginners can learn from the agreement.
ask100
- 时钟同步模块：通过时钟同步模块，将模拟前端提取的时钟信号和数据进行同步，使得数字后端可以正确读取数据。-Clock synchronization module: The clock synchronization module, the analog front-end of the clock signal extraction and data synchronization, making the number of back-end data can be read correctly
15252uP(1)
- 这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
verilog
- 可综合的Verilog语法（剑桥大学，影印）-Can be integrated Verilog syntax (Cambridge, photocopying)
USBverilog
- verilog USB程序，经过实践调试，并且都能成功实现-verilog USB procedures, debugging practice, and can be successfully achieved
signal
- verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
cpu(FinalWithYS)
- verilog实现的八位CPU，包括乘法、除法以及多种寻址方式。代码中包括测试模块，可以直接在试验箱上运行。-verilog to achieve the eight CPU, including multiplication, division, as well as addressing a variety of ways. Code, including test modules, can be run directly in the chamber.
I2C_receiver
- 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code