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SigCylCPU
- 单周期cpu的设计实现在VHDL中的verilog中实现。 -Design and implementation of single-cycle cpu in VHDL to implement the verilog.
MulCylCPU
- 多周期cpu在VHDL中的verilog实现-More cpu cycles in the verilog implementation in VHDL
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
AVR_Core
- AVR 单片机内核处理器vhdl代码，用fpga设计的avr cpu核，主要供fpga学习者参考用-AVR microcontroller core processor vhdl code, using fpga design avr cpu core, the main reference for learners fpga
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
MODE
- 基于VHDL的CPU设计 计算机组成系统-VHDL-based design of a computer system consisting of the CPU
cpu_verilog_vhdl
- CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
CPUexperiment1G
- vhdl课程设计的CPU程序，实现了CPU的完整功能，最终评为优秀-vhdl program curriculum design of the CPU, the CPU to achieve the full functionality of the final good as
ALU
- ALU CPU内部运算器 这个是ALU内部个模块的VHDL程序和原理图-ALU THE ONE PART OF CPU .ZHIS PART INCLUDE VHDL
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
CPUtest
- 完成一个CPU的设计，采用VHDL编写，含有图像分析-failed to translate
CPUwithout-cache
- 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
ALU
- VHDL设计的ALU，可以添加到CPU的编写者-VHDL lanuage design for ALU
1_ADDER
- ＣＰＵ内部的加法器用ｖｈｄｌ语言在可编程逻辑器件上的实现-Within the CPU is VHDL language addition in programmable logic devices for fulfillment
4_COMP
- ＣＰＵ内部的比较器用ｖｈｄｌ语言在可编程逻辑器件上的实现-The comparison of the CPU internal used VHDL language in programmable logic devices for fulfillment
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
test_cpu
- 自己编的小型CPU，可执行简单的代码，作为对开发CPU的尝试。里面包含ROM和CPU。CPU通过状态机执行指令。在Modelsim中仿真通过。-Small VHDL CPU,as a example for developing CPU. It is simulated by Modelsim.