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neek_alternate_sd_card_controller
- This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a
cycloneIII_3c120_dev_niosII_standard
- 该源码是关于FPGA片上系统sopc的nios处理器设计，他实现了led，lcd以及Internet网络各种功能，源码已经测试通过，读者可以使用-The source is on the FPGA chip on the system sopc the nios processor design, he realized the led, lcd, and Internet networking features, source code has been tested, the reader
Altera_Cyclone_III
- Protel99库 Altera_Cyclone_-Protel99 Library Altera_Cyclone_III
cycloneIII_dev
- cycloneIII_3c120_dev_kit-v7.2.3_CDROM cycloneIII_3c120开发套件的全部CD资料-cycloneIII_3c120_dev_kit-v7.2.3_CDROM cycloneIII_3c120 all the CD information Development Kit
EP3C120-LCD
- 应用verilog语言编写的在ALTERA-CYCLONE III 开发板1602上面显示字符-Application verilog language characters shown above in 1602
cycloneIII_3c25_start_my_first_fpga
- Q11 cyclone III 3c25 start my first fpga for cyclone 3 starter board altera
AN521_design_example
- Cyclone III Active Parallel Remote System Upgrade Reference Design -The Cyclone III Active Parallel Remote System Upgrade Reference for the Design
pld_Tetris
- 基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行，屏幕倒置，分数显示，vga接口，键盘接口等功能-Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface.
dds-5
- 基于FPGA cyclone III EP3C16F484C6的dds正弦波发生器，频率可调-the dds sine wave generator based on the FPGA cyclone III EP3C16F484C6 , frequency adjustable
FPGA_USB
- vhdl cy7c68013 fpga cyclone III 数据采集-vhdl cy7c68013 fpga cyclone III data acquisition
fpga_sram_read_write
- CYCLONE III读写ISSi6V25616 SRAM的测试程序，直接编译下载程序到板子上运行-CYCLONE III ISSi6V25616 SRAM read and write the test program, compiled directly download the program to run on the board
check_display
- 基于FPGA的直流电机测控仪，用的是quartus，完整的项目，如果用的同一块板子，cyclone iii EP3C80F380C8,管脚都分配好了。-FPGA-based DC motor Monitor, is Quartus complete project If you are using the same board, Cyclone III EP3C80F380C8 pins are allocated.
DE0_VGA
- FPGA的视频接口程序 核心芯片是cyclone III EP3C16F484-FPGA-video interface program
clockend
- 基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。-QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual ti
CD1_MT9M111_DISPALY
- 使用Altera fpga cyclone III系列EP3C16对摄像头MT9D001的驱动，并可以在VGA显示器上实时显示。使用quartus 10.0打开，注意不要使用中文路径。-Using Altera fpga cyclone III series EP3C16 MT9D001 the camera driver, and can be displayed in real time on a VGA monitor. Using quartus 10.0 open, be carefu
Standard
- Cyclone III standard Embedded Evaluation sopc
cyclone3_DE0_EP3C16F484handbook
- DE0 开发板的用户手册（EP3C16F484）实例 verilog-DE0 cyclone III EP3C16F484 handbook
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
Protel99_lib_ALTERA
- protel cyclone iii系列 原理图，PCB
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA