搜索资源列表
DDR_allegro
- 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
20060510191318991
- ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Hardware_Test_Programs
- ccs下对dm6446的测试程序，能够检测ddr,nandflash,uart,usb等硬件电路的裸板测试代码，包含库文件，板级gel文件，开发环境在TI ccs3.3下。-ccs on DM6446 testing procedures can detect ddr, nandflash, uart, usb hardware such as the bare circuit board to test the code, including library files, board-leve
DDR_SDRAM
- 利用fpga读写ddr的源代码 实测可以使用-Ddr use FPGA to read and write the source code can use the measured
DDR
- leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
K4H511638脰D
- Data Sheet 512Mb D-die DDR SDRAM Specification
testbench
- ddr sdram controller datd module source code
S3C6410X_Type_Circuit_Design_Guide_rev1.00
- S3C6410 線路設計時一定要參考的文件,尤其是DDR Layout guide一定要看.以免開發出的板子不能動.-S3C6410 circuit design must read this documents, especially DDR Layout guide. To avoid your board can not run in high speed.
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
DDRSDRAM
- DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
OXE800SE_OXE800DSE
- SATA NAS SOC，200MHz ARM926EJS核 SATA接口的NAS用处理器，集成USB2.0 HOST接口，Ethernet控制器，DDR SDRAM控制器，PCI HOST接口，可以扩展PCI外设。-SATA NAS SOC，NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller，USB2.0 HOST controller，Ethernet MAC controller，DDR SDRAM c
DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
DDRSDRAM
- DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
TM4600-4100-AS1690_Sch_zl2(DDR)_3
- Quanta ZL2 motherboard schematic
512Mb_ddr_Modules
- DDR and DDR DIMM Controller
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
DDRSDRAM
- DDR SDRAM设计及调试经验总结.pdf
sdram32
- DDR SDRAM source verilog source codes
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
DDRctroll
- ddr 的fpga 控制器的实现 仿真正确-ddr controller fpga to achieve the correct simulation