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dtrigger
- 分频器，对输入时钟进行分频,可以用来驱动电机，或者用作其他需要时钟源的外设的驱动信号-Divider, devide the input clock frequency to another frequence clock signal
vfxc
- 一种实用的除法器,对于初学者很大帮助，代码不大，精简好用。-A practical divider, very helpful for beginners, the code is not streamlined easy to use.
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
VHDL-
- VHDL语言 有限状态机交通灯的设计 分频器模块的设计-Finite state machine design language VHDL design of traffic lights divider module
clockdiv_teste
- Clock division program write in Verilog with selected divider (32 bits)
fp
- 实现60MHZ到40KHZ的分频，分频后壳实现外部晶振和内部晶振的时钟统一。-60MHZ to achieve 40KHZ divide the shell to achieve external crystal oscillator and internal clock divider after unification.
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
counter
- 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21
Airtight.tar
- 测试台的工控程序，主要控制继电器，LED灯，以及分频器-IPC test bed program, the main control relay, LED lights, and a frequency divider
divcnt
- 基于Lattice XO2系列的简易分频器-Based on Lattice XO2 series of simple divider
Half_Frequence
- 本程序基于VHDL语言，设计分频器，其中包含半整数分频占空比不为50 奇数分频占空比为50 任意小数分频 -The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional
LED-blinks
- 选择不同的时钟源，使 P3.7 连接的发光二极管闪烁。 （1）使用 XT2 时钟源，8MHz 频率，用定时器 A 分频，产生 1s 脉冲，使 P3.7 引脚的发光二极管闪烁。-Choose different clock sources, so P3.7 connected LED blinks. (1) using the clock source XT2, 8MHz frequency divider with the timer A, the pulse generating 1s,
divp5
- fpga上实现的最小是0.5分频的任意分频器-FPGA to achieve the minimum 0.5 hours are arbitrary frequency divider
fenpinjishuqi
- 本文档包括实现分频的方法以及奇数分频偶数分频的verilog代码 经测试可用-This document includes methods to achieve divide and even the odd divider divider verilog code used by the test
vc
- 利用C语言设计出一个具有16分频、8分频、4分频和2分频功能的分频器-Using C language to design a divide with 16, 8, 4 and 2 frequency divider divider function
eg_xianxing
- 线性反馈移位寄存器产生伪随机序列可编程分频器- Linear feedback shift register programmable divider generate pseudo random sequences
IntegerDivider
- 整数除法器 无负数复数 期末项目 verilog-integer divider
phase_add
- 分频器，实现任意频率的分频，只需修改频率控制字,已经经过多次验证-Divider to achieve any frequency divider, simply modify the frequency control word, has been repeatedly verified