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fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
Filtro
- Digital filter in VHDL
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
ellip-(1)
- 基于FPGA的椭圆滤波器 采用VHDL语言 使用quartus仿真-Elliptic filter FPGA-based simulation using VHDL language quartus
Correlator22BIT
- gps接收机基带信号处理的相关滤波器设计vhdl源程序，已经在实际产品中得到应用与验证，请放心使用。-Correlation filter gps receiver baseband signal processing design vhdl source code, has been applied and verified in the actual product, the ease of use.
FIR
- this file is vhdl code of fir filter
bayer
- verilog/ vhdl code for processing the bayer filter signal
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
New-Text-Document.bmp
- basic fir filter implementation vhdl code
FirFilterChol
- 在FPGA利用vhdl实现了32阶FIR滤波器。已经我利用了在几个对象。-In FPGA using VHDL to achieve a 32 order FIR filter. I ve used in many objects.
xiaosong-fpga
- FIR数字滤波，亲自测试，都是源码，希望可以帮到大家，谢谢，谢谢！大家要好好学习呀，学习好VHDL(FIR digital filter, personally tested, are source code, and I hope to help you, thank you, thank you! We should study hard, good study, VHDL)
15010120041_高瑞雪_lab2
- 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi