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FIR有限冲击响应滤波器verilog代码和测试-FIR finite FIR filter verilog code and test
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FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
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一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
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基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
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一个不错的数字滤波器verilog源码，希望大家能用的上-A good digital filter verilog source
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xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
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verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
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利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
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最长的那个句子，求sum的赋值语句就是FIR滤波器的计算过程，将二进制乘法转化为移位运算。对于小数点后的乘数是向左移，小数点前的乘数是往右移位。
-The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the deci
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verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
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基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
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FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
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使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog
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四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
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FIR滤波器的verilog实现，包含testbench，以及设计文档，文档里面详细介绍了滤波器系数的求取-FIR filter verilog implementation, including testbench, and the design document, the document which details the filter coefficients to strike
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VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
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VERILOG CODE FOR 2D FIR FILTER
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用Verilog HDL实现FIR滤波器的功能，文件包括Verilog HDL的源代码。-Using Verilog HDL realize the FIR filter function, the file includes Verilog HDL source code.
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48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
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FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
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