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用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
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Verilog 编写的fir滤波器，可以实现fir滤波器的功能-Verilog prepared by the fir filter can achieve fir filter function
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个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR,DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
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高通滤波器的verilog实现，对初学者设计FIR有好处，分布式算法-Verilog implementation of high-pass filter, FIR design is good for beginners, distributed algorithm
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使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
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基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
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FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
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用verilog语言编写的一个FIR滤波器的程序-Verilog language with a FIR filter process
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用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
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一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
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基于Verilog的FIR滤波器的设计，该代码包含完整的工程，可以利用quartus软件直接运行-Design of FIR filter based on Verilog, the code contains a complete project, can use quartus software to run directly
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This is verilog code for FIR Filter with testbench availble.
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This a verilog code for FIR filter works good on linux and windows platform-This is a verilog code for FIR filter works good on linux and windows platform
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fir滤波的补码变换，用于verilog程序-fir filter complement conversion program for verilog
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使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
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A classic FIR filter implemented using Verilog HDL on the Xilinx software-A classic FIR filter implemented using Verilog HDL on the Xilinx software
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DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
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FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
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用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
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经典的verilog语言实现转置型FIR滤波器的代码(Code of Inverted FIR Filter Implemented by Classical Verilog Language)
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