搜索资源列表
Mealy-FSM
- 这个程序描述的是模拟并实现了米里有限状态机的功能的实例-This procedure describes the simulation and Mealy finite state machine instance
fsm
- brief finite state machine source code.
FSM_3blocks
- 经典3段式有限状态的verilog HDL描述，在modelsim 中仿真通过。-A classical FSM of three paragrahs, which is described by verilog HDL and simulated in modelsim successfully.
Verilog-FSM(TSC)
- Finate State machine
AntAIBaseOnFsm
- 用有限状态机(Fsm)实现《WINDOWS游戏编程大师技巧》人工智能蚂蚁寻找食物范例-Ant AI base on Finite State Machine.
decode
- 使用FSM控制，完成32位数据的decode，对DATA_PATH进行监测，Load Return addr from Stack into PC-Using FSM control, complete 32-bit data decode, for DATA_PATH monitoring, Load Return addr from Stack into PC
I2C_Slave
- I2C slave IP core，内含此IP core的完整code，详细的式样说明,详细的状态机说明-I2C slave IP core, include complete code of this IP core, and the detailed specification, the detailed FSM.
fsm
- 检测连续3个1的状态机的VHDL代码，输入11111则输出00111，ISE可以编译仿真，运行-Detecting consecutive three one state machine VHDL code, enter 11111 Output 00111, ISE can compile simulation run
ethernetpreempt
- In digital communication, a special synchronization pattern, known as a preamble, is used to indicate the beginning of a packet. For example, the Ethernet I1 preamble includes eight repeating octets of "10101010". We wish to design an FSM that genera
FSM111
- Demo about FSM-verilog for starter
AXI_Master_FSM
- AXI Master, is implement with FSM
DS1302
- 控制DS1302时钟芯片,包括对芯片读写的底层代码，控制代码，加入了指令，使其成为了独立的模块。-control the DS1302 clock chip,including the root code,FSM,and some instructions,which can be independent from other modules.
tiaoshi_18_outVector_FSM
- omnet++模拟环境中的FSM状态机仿真代码-omnet++ simulation environment FSM state machine simulation code
qfFSM_for_javascript_v1.1
- qfFSM_for_Javascr ipt，一份js实现的有限自动机类库，用于对流程建模，可与UML状态机图对应编码。-qfFSM for Javascr ipt, one library for FSM.
qfFSM_for_java_v1.0
- qfFSM for Java，一份有限自动机类库，Java语言版本。用于对流程建模，实现与UML状态机图对应。-qfFSM for Java, one library about FSM.
gcd_power
- 用硬件描述语言实现求最大公约数，使用FSM-using hdl implements the gcd with gsm
Qcalc
- 一种基于FSM框架的计算器状态机源码，非常有利于大家对状态机的理解-status machin
Document-on-Intelligent-Traffic-Light-Controller.
- Traffic Light Controller FSM and Code
t3_sdram
- 完成sdram读写操作，并附有测试脚本文件，已通过后仿验证。该程序主要包括上电初始化模块，刷新模块，读、写模块等，并采用FSM控制所有模块，完成数据的读写操作-Sdram read and write operations to complete, with a test scr ipt file has been verified through simulation. The program includes power-on initialization module, refresh m
fsm
- 有限状态机的一种实现框架，更健壮，更易于表达。-An implementation framework of finite state machines, more robust and easier to express.