搜索资源列表
traffic_cntrl
- FSM based traffic light controller
FSM
- 经典有限状态机嵌入式C源码，采用事件、状态构成的状态迁移表实现-Standard finite state machine embedded C source code, using the state transition table of events, the state to implement
Sequence-Detector
- 序列检测器，开写为两个always语句，即为两段式有限状态机。将组合部分中的判断状态转移条件和产生输入再分开写，则为三段式有限状态机。 二段式在组合逻辑特别复杂时适用，但要注意需在后面加一个触发器以消除组合逻辑对输出产生的毛刺 。三段式描述方法虽然代码结构复杂了一些，但是换来的优势是：使FSM做到了同步寄存器输出，消除了组合逻辑输出的不稳定与毛刺的隐患，而且更利于时序路径分组，一般来说在FPGA/CPLD等可编程逻辑器件上的综合与布局布线效果更佳。-Sequence Detector
fsm
- -Hardware assisted single cycle bswap (Use Case of ARC custom instrn).Several ways of Endian-Swap Emulation for ARC.
tx__fsm
- 这是一个描述FSM的代码，是我project项目的一部分希望共享给大家，也和大家共同进步-This is a descr iption of FSM code is part of my project project hope for everyone to share, too, and common progress
TaskScheduler
- Arduino 任务管理器库，可以用它完成有限状态机的功能-Arduino taskscheduler lib,do sth like FSM function
ModelSim_linux_crack.tar
- Implementation of a simple fsm
uart2bus_latest
- uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP
swfsm
- stopwatch的FSM状态机的代码，可供初学者学习参考如何编写状态机-the finite state machine vhdl code for the simple stopwatch file
lab03-.tar
- vhdl about 3 stage control block of cpu-vhdl control block of the 3 stage cpu(FSM)
FSMpart2
- Verilog implementarion of FSM. Solution for altera s lab 7 part2.
part3FSM
- Verilog FSM implementation for altera s lab(part 3 of lab 7).
FSMpart4
- Verilog FSM implemetation for altera s lab 7(part IV) for de2115 fpga.
FSMpart5
- FSM Verilog implementation of the final part of lab 7 of altera s verilog tutorial for de2115 fpga.
controller
- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang C
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize
FSM
- 这是一个有限状态机的设计，并且用来测试一个学列，七段数码管输出检测序列的值，有限状态机用三段式编写。- This is a finite state machine design, and used to test a school, seven-segment digital output detection sequence value, the finite state machine with three-stage preparation.
Seq_det_binary
- FSM Seq detector in binary encoding
Seq_det_gray
- Seq_detector in gray encoding. FSM modelling
verilog
- VITERBI DECODER MODULE This module implements the FSM and instantiation of all the modules used for Viterbi decoding.