搜索资源列表
AUDIO
- TLV320AIC23B的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-TLV320AIC23B the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
IIC
- 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
pwm
- 用VHDL语言 描述 生成pwm的 IP核-Pwm using VHDL language to describe the generation of IP core
ug_vip
- Altera公司原版设计手册，关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores i
LCD12864IP
- 12864的IP，在艾米电子工作室的nios开发板上可执行-12864 of the IP, in the electronic studio nios Amy executable development board
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
PWMcore
- 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.
VGA
- 应用VEROLOG HDL编写的VGA的IP核，可用于SOPC BUILDER中-the control of the i2c bus
cpu86
- CPU86 - Free VHDL CPU8088 IP core Copyright (C) 2005-2010 HT-LAB Quick run: 1) Open a DOSBox/Cygwin shell 2) Navigate to the web_cpu88/Modelsim directory. 3) Execute run.bat See website for more details. The CPU86 cor
fft_32K
- This example describes a 32K-point fast Fourier transform using the Altera FFT IP MegaCore. 描述了一个32K的点快速傅立叶变换（FFT） 。
8051
- 51ip核 用vhdl编写 在迅雷上下载-51 ip core write with vhdl
fftip
- 2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
lwip
- Design and Implementation of the lwIP TCP/IP Stack
ethmac
- ethmac IP CORE VHDL IN QUARTUS-ethmac IP CORE VHDL IN QUARTUSII
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
freedev_ps2
- 自由电子科技的PS2键盘的avalon外设ip core-Free electronic technology avalon PS2 keyboard peripheral ip core
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
xapp1022
- xilinx FPGA利用MET平台测试PCIe IP核的说明文档与源文件、-xilinx FPGA platform testing by MET PCIe IP core documentation and source files
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
source
- SDRAM控制器源代码，是ALTERA公司的IP源核，很好很强大-SDRAM controller source code, very very strong