搜索资源列表
bjautiful_beautiful_beautiful
- 很不错的java特效,包括漂亮时钟,水波,抖动-Good Java effects, including beautiful clock, water wave, jitter
ievhnologyyour
- To achieve patterning and jitter technology, and bmp2txt-To your patterning and jitter technology, and bmp2txt
KEY
- 实现按键消抖级检测,通过检测按键,实现LED灯的亮或灭(To achieve the key jitter level detection, through the detection button, LED lights to achieve brightness or extinction)
ienzy
- Implementation pattern and jitter technology, as well as bmp2txt command-line compilation process is as follows
piopositionsHDLC
- To your patterning and jitter technology, and bmp2txt
AD9512_coe
- AD9512 提供多路输出时钟分配功能,输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性,能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the cl
AD9512_ISE
- AD9512提供多路输出时钟分配功能,输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性,能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clo
至简设计法--按键消抖
- 按键消抖 工程说明 在系统设计中,消除按键抖动的方法五花八门,无论是硬件电路和软件设计都十分成熟。在本项目中,我们将用Verilog语言给出具体实现过程,设计一个程序来检查键值,有效滤除按键抖动区间20 ms的毛刺脉冲。 案例补充说明 在本案例中,我们使用Verilog HDL语言对按键消抖进行了设计,在这个过程中,我们可以了解到不同触发器有不同的工作原理和约束条件,即便是简单的一个按键功能,也有不可忽视的抖动过滤程序,这些都是在以后的设计工作中需要注意的。(Keystroke ditheri
AD9854代码
- 300 MHz内部时钟频率 集成的12位输出DAC 超高速,3 ps RMS抖动比较器9854代码(300 MHz Internal Clock Rate Integrated 12-Bit Output DAC Ultrahigh-Speed, 3 ps RMS Jitter Comparator9854code)
key
- 51单片机新型按键扫描,不用10ms延时消抖,实时性大大提高。每个按键有长按短按功能,采用结构体对象化编程,增加按键极度方便。(The new key scan does not use 10ms delay to eliminate jitter, and the real-time performance is greatly improved. Each button has a long press, a short press function, the use of structur
monifashu
- 用VHDL实现了对外部信号的消抖功能,将信号平稳无毛刺的接收,同时模拟一个时钟频率发送一段数据(The function of eliminating jitter of external signal is realized by VHDL, and the signal is stable and receive without burr)
AD9883 iic_v1.0_for_sim
- 程序用于配置AD9883芯片寄存器,采用iic协议。 FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Proces
GMMmatlab程序
- 混合高斯模型,用于背景变化无抖动的目标的前景提取(The hybrid Gauss model is used for foreground extraction of background invariant targets without jitter)
卡尔曼
- 实现视频去抖动,利用了卡尔曼滤波更稳定,个人认为不错(To achieve video jitter, the use of the Calman filter more stable, personally think that good)
dou
- 进行仿射变换,实现视频的去抖动,没有卡尔曼滤波,可以实现,有问题找我(Affine transformation, the realization of video jitter, no Calman filter can be achieved, there is a problem to find me)
基于MATLAB的升降式抖动机构运动仿真
- 非常好用的基于MATLAB的升降式抖动机构运动仿真(Motion Simulation of Lifting Jitter Mechanism Based on)
video-stabilization
- 使用matlab编写的视频消抖的程序,效果不错,可以试试(Matlab written using video jitter elimination program, the effect is good, you can try)
bayer抖动算法
- 抖动算法分为随机抖动算法和有序抖动算法。随机抖动算法随机产生一组模板方阵数列,随机数的产生期间在图像的最小灰度和最大灰度之间。有序抖动算法是人为地设置一些模板值进行匹配操作,主要有分散性抖动算法(Disperse Dither)和聚集型离散算法(cluster Dith神两种。分散型以Bayer有序抖动算法为代表。后来Ulichenay在以上两种算法的基础上,提出了局部聚集整体分散的抖动算法。(Dithering algorithm is divided into random ditherin
lab3
- 在ns-2中实现lab3的仿真,以及分析网络的吞吐量、时延、抖动等功能(ns-2/througput/delay/jitter)
pll_test
- PLL,即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率,相位的时钟信号。所以,一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中,时钟系统的FPGA高速的设计极其重要,一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource