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ethernet_tri_mode_rtl.tar
- 以太网控制器verilog，含有mac,mii接口
ethernet_tri_mode.tar
- 用FPGA verilog hdl实现千兆以太网MAC。
ethernet_controller
- 以太网控制器MAC的verilog代码，已经过验证，可以用。-Ethernet Controller
test_mac_loopback
- 用来测试MAC地址回环的VERILOG程序，可以继续完善它-Loop used to test the MAC address of the VERILOG program, you can continue to improve it
smii_latest.tar
- SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following r
61EDA_D691
- Mac的硬件描述实现,用FPGA完成MAC的控制。-Verilog for MAC descr iption
Xilinx
- Demux modules and test simulations with various combinations of input and output vectors.I am new to Verilog.I am learning it through a electronic system design course on my college.I am interested in downloading a single .zip file from this site,Ver
MAC_controllor
- mac控制器的代码，包含仿真程序,用verilog HDL语言实现。-the verilog code of mac controllor and with the testbench
ethernet_test
- Verilog implementation of ethernet mac 100mbps test
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(F
eth
- 用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码-With digital logic language to describe Ethernet
ethernet.tar
- verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
RTL
- Booth radix2 MAC UNIT In verilog
eth_Management_interface
- FPGA verilog simple MAC 源码-FPGA verilog simple MAC source code
verilog_mac
- 该文档详细描述了以太网mac层的功能与实现，里面包括了verilog程序-The document describes in detail and implementation of Ethernet MAC layer functions, which includes the Verilog program
ethmac10g_latest.tar
- ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！-ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project!
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
MACswitch
- 基于VERILOG的MAC控制器代码，比较有参考价值，可以看看。-The MAC controller based on VERILOG code, more reference value, can have a look.
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.