搜索资源列表
lisa-vhdl2va
- 通过modelsim仿真检测matlab生成滤波器效果。-Generate the filter through matlab and simulated by modelsim.
Md5Sopc
- 在Altera平台上实现Md5算法的IP核 modelsim进行MD5硬件代码的仿真和测试 quartusII 和nios软件实现ip核和驱动程序 已经测试程序的仿真和测试 代码调试通过 -Md5 algorithm simulation and test implementation in the Altera IP core platform modelsim the MD5 code simulation and test hardware and quartusII ip nios so
booth_multiply
- 布斯乘法器，采用verilog语言实现 经过modelsim仿真-Booth multiplier using verilog language through modelsim simulation
18b20_code
- 利用DS18b20温度传感器设计的温度计，温度值在数码管上显示。包括源代码，modelsim仿真与DS18B20相关PDF资料-Temperature sensor design use DS18b20 thermometer, the temperature value is displayed on the digital control. Including source code, modelsim simulation and DS18B20 information related t
ISE_Modelsim-
- ISE与modelsim开发环境进行联机，设置经验的总结-ISE and modelsim online development environment, set and experience in
textio03
- 在QUARTUS II 下用 MODELSIM 仿真的例子，用TEXTIO文件进行仿真，带读取数据的文本文件，注释也比较详尽。对初学仿真有帮助。-In QUARTUS II with MODELSIM simulation examples, simulation with TEXTIO file, a text file with read data, comments are more detailed. Simulation helpful for beginners.
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
myfir
- VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
vhdl--based-ontesebench
- modelsim环境基于vhdl语言tesebench书写-vhdl modelsim environment based on written language tesebench
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
I2C_control
- I2C两线式串行总线的控制端的verilog源代码，经过编译和modelsim仿真后是正确的！-Two-wire I2C serial bus control terminal verilog source code, after compiling and modelsim simulation is correct!
220model
- 220model 与 altera mf的库 用于fpga的modelsim仿真过程中添加到工程里面-220model altera mf fpga modelsim
or32-uclinux
- OR32arm内核，可进行modelsim仿真并运行UCLINUX操作系统-OR32arm kernel, can be modelsim simulation and run the operating system UCLINUX
micron-lpddr-sdram-lpddr_model
- modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
I2C
- I2C总线控制器的VHDL代码、ISE工程文件、ModelSim仿真环境等-I2C bus controller VHDL code, ISE project file, ModelSim simulation environment
Modelsim_use
- 这个文档主要讲解了一些快速入门Modelsim的一些知识，有一些详细操作过程。-This document is intended to explain some of the Quick Start Modelsim some knowledge, some detailed operation.