搜索资源列表
FlashFS
- This is an RTL Flash File System example. The data captured from the serial interface is stored to a file. You can read the file, rename it or delete it from the flash. You can also display the file directory list.
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)
RTL8723BU
- rtl 8723bu驱动代码，包含蓝牙及wifi(softap sta bluetooth)
Master SPI的Verilog源代码(包括文档 测试程序)
- SPI接口的从机实现（利用verilog HDL语言）(Slave implementation of SPI interface (using Verilog HDL language))
AHB_SMSS
- ahb single master single slave rtl design
eetop.cn_simple_spi
- spi 模块代码 RTL verilog(spi rtl code)
pipelined_fft_128_latest.tar
- RTL IMplementaion for the project
spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
02047389
- 蓝牙的一个ip RTL 核,不知道对大家有没有用？谢谢,()
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
rtl8188eu_20160706
- 该驱动可以直接在全志A13平台上跑的WIFI驱动 型号是rtl 8188eus(The driver can run directly on the full A13 platform and the WIFI driver model is RTL 8188eus)
REALTEK WIFI DRIVER
- REALTEK WIFI DRIVER chipset RTL8188EUS,RTL8189ES
Synopsys SCL 10.9.3
- 后端综合软件design compiler将verilog源码，RTL文件转变成电路并实施优化
ambartl
- amba总线的rtl代码，仿真用，不可综合。(AMBA bus RTL code, simulation, can not be integrated.)
RTL8812AU_linux_v4.3.20_16317_20160108
- RTL88x2 wifi无线网卡驱动，适用于linux2.6.x 3.x平台，使用平台指定交叉编译工具编译即开使用，编译为ko文件(The RTL88x2 wifi wireless card driver is applicable to the linux2.6. X 3. X platform, which USES the platform to specify the cross-compilation tool to compile and use, and compiles the
8051
- The resource code of The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system
si四位加法器
- 内含三个普通的四位加法器，adder，adder4-2，adder4-3(library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity full_adder is port( a,b,ci :in std_logic; s,co :out std_logic); end entity; architecture rtl of full_adder is begin s&
modol
- 蓝牙的一个ip RTL 核,不知道对大家有没有用？谢谢,()
8051Core
- 8051 Core Verilog RTL IP Code
rtl
- 实现AD7606数据采集，基于xilinx的6系列(Realization of AD7606 data acquisition)