搜索资源列表
code
- 一个8位微处理器的VHDL代码以及testbench-8-bit processor VHDL
myself_uart_vhdl
- 自己写的，对串口的VHDL描述，有完整testbench，特别是详细的功能说明和注释。-Wrote it myself, on the serial port of the VHDL descr iption of a complete testbench, in particular, detailed functional descr iptions and notes.
i2c_core
- I2C core 及testbench（verilog）-I2C core and testbench [verilog]
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Writing_Efficient_Testbenches
- vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
cordic_generic
- 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version,
tcc_cdma
- full testbench design including random number generator, the tcc encoder, the tcc decoder and some control logic.
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
bin2bcd
- Binary to BCD converter
shift
- Simple shift register with testbench in vhdl
uart_testbench
- opcore.org "uart16550" 项目的testbench-test bench of "uart16550" project
mainboard_model
- FPGA与dSP的接口，包括testbench部分，以及实现-DSP interface with the FPGA, including part of testbench, as well as the realization of
COMPRESSION
- Simple LZW image compression implemented on Spartan-3e starter kit using Xilinx9.2 and Modelsim for testbench simulation.
santhosh_multiplier
- This has verilog code for multiplication.. It will be useful for beginners of verilog.. The testbench for multiplier is also attached with the file setup. Comments are welcome
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
mini_aes_latest[1].tar
- AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL