搜索资源列表
SinglePeriodCPU
- verilog语言书写，单周期CPU源码-single period CPU
fivevhdl
- 5中cpu的程序，包含arm4，arm6，arm7等程序，的verilog实现-5 cpu procedures, including arm4, arm6, arm7 and other procedures, the verilog implementation
MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
061110061
- 在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令-Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions
cpu8
- 用Verilog仿真8条基本指令的CPU，是学习编写多条指令CPU的基础-Verilog simulation with the basic instructions 8 CPU, CPU to learn the basis for the preparation of multiple instructions
PipelinedCPU
- 用Verilog语言实现的流水线CPU设计，大家可以参考一下。-Using Verilog design language of the line CPU, you can reference.
risc8
- verilog risc8 cpu-verilog risc8 cpu
lab_simulation
- verilog 开发的，模拟CPU流水线操作的工程设计。-verilog developed to simulate the engineering design of CPU pipelining.
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
MulticlockCPU.tar
- verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
LIP2321CORE_cpu_local_ram
- CPU Local RAM Verilog Module
LIP3001CORE_cpu
- CPU Verilog Module source code
rom_pld_top
- PC CPU 大廠 Intel 所使用的 Verilog code-Intel CPLD Verilog code
Leg8
- 待商业化的8位高速cpu芯片设计，verilog语言编译通过，ISE平台完成-To be commercial cpu 8-bit high-speed chip design, verilog language compiler, ISE platform to complete
Verilog_cpu-_example
- 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
risc8
- 基于verilog的8位risc-cpu源码，modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
SigCylCPU
- 单周期cpu的设计实现在VHDL中的verilog中实现。 -Design and implementation of single-cycle cpu in VHDL to implement the verilog.
MulCylCPU
- 多周期cpu在VHDL中的verilog实现-More cpu cycles in the verilog implementation in VHDL