搜索资源列表
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
mini_cpu_verilog
- 用verilog写的简单的CPU，有详细注释-Use verilog to write a simple CPU, with detailed notes
ece5742010hw9CPU
- 用verilog语言实现CPU， 其中包括几个不同的模块，每个模块中间由总线进行连接-implement the CPU using Verilog language, including the memory, controller,data path, the logic unit.
MIPS_cpu_verilog
- 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
cpu_verilog_vhdl
- CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现，MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
single_cpu
- 单时钟CPU在XilinxISE 10.1的全代码，由Verilog语言描述-Single-cycle CPU in Verilog developed on XilinxISE 10.1
MIPSCPU
- 用verilog描述语言实现的MIPS32位单周期CPU。-Verilog descr iption language with the MIPS32-bit CPU.
cpu_fsm.tar
- cpu的verilog的不同状态的状态机实现程序编写-write or reset or read or delay of CPU by verilog
RSIC_CPU2
- 这是一个用verilog编写的RSIC CPU模型，几个必要的模块都已经齐全，有兴趣的可以再完善更多的功能-This is a verilog written RSIC CPU model, several necessary modules are already complete, are interested in more features can be further improved
RISC_CPU
- 一个简单CPU设计，可以让读者在计算机组成原理和verilog语言方面受益-A simple CPU design, allows the reader to the computer principles and Verilog language benefit
MIPS
- 用verilog语言描述的CPU各部分及相关链接-It about CPU s component and relationship which use verilog
SRC
- 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
simpleCPU
- 一个简单的多周期CPU的实现，verilog语言实现，结构较简单，欢迎分享-A simple multiple CPU,based on language verilog
poc
- verilog 写的POC接口代码。测试波形功能通过。内有波形模拟CPU以及仿真文件。-A poc module written by verilogHDL.Can be used in communicating with MCUs. The simulate wave file is already inside.
PipelineCPU2
- Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti