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pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
code
- cpu的主要功能部件verilog简单代码-main features of cpu verilog simple code
SAYEH
- Verilog 数字系统设计---综合、测试平台与验证 .书中源程序-cpu in verilog descr iption. include C language source
demo_2012_2
- KD_CPU,8位实现基本功能的cpu，基于verilog-KD_CPU,8bit CPU with basic functions, base on verilog
Dragon-Heart_VERILOG.doc
- 神州龙芯cpu的verilog设计规范，本规范适用于下列三种 Verilog代码文件的编写：1）可综合逻辑部件；2）虚拟部件（Virtual Component--VC）；3）测试模块（testbenches）。-The verilog design specification of BLX cpu
code_VHDL
- 无流水无cache的cpu代码，基于verilog，CPU 芯片的主频是 15.3MHz,FPGA 器件的资源占用率为 28 -cpu code with no water nor cache
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
control_pipeline.zip
- Verilog components for a pipelined cpu simulation,Verilog components for a pipelined cpu simulation
SingleCycleCPU.zip
- A complete single cycle cpu written in verilog. (Including test modules),A complete single cycle cpu written in verilog. (Including test modules)
Multi
- A Complete Multicycle CPU Written in Verilog Lang.
para_serial
- 利用Verilog语言实现串并转换和并串转换，方便CPU和单片机之间通信 -Verilog to implement a serial-to-parallel conversion and parallel-to-serial conversion, to facilitate communication between the CPU and the microcontroller
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
DW8051
- dw8051 verilog 源代码，包括cpu的各个模块定义，实现。可综合IP软核-dw8051 verilog
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
SC_CPU
- single cycle CPU element design with Verilog
cpu_cache_interrupt
- verilog写的CPU 五级流水 带cache 中断-the the CPU five water with verilog to write cache interrupt
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
MIPSCPU
- 用verilog描述一个mips体系结构的cpu，分别用c语言mips汇编语言写了一段程序，翻译成机器码可以再cpu上运行。仿真结果三者完全一致。-Mips architecture cpu with verilog descr iption c language mips assembly language to write a program, translated into machine code can then cpu running on. Simulation results e
cputest
- 通过verilog语言设计的简单CPU，可完成加减乘除和算数逻辑移位功能。-By verilog language design simple CPU, to be completed by addition, subtraction, and arithmetic logic shift function.