搜索资源列表
paralleladder
- This a verilog source code for parallel adder-This is a verilog source code for parallel adder
FullAdder
- full adder verilog de2-70
HW-02-13210140
- Verilog code adder for add 2 16bit in parallel-adder for 16bit used to add two bits in parallel. this code in verilog languanger
module002268.tar
- this verilog code of adder-this is verilog code of adder
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
quanjiaqi
- 使用verilog HDL实现全加器的功能-Use verilog HDL to achieve full adder function
4weichaoqianjinweiqi_verilog
- 四位超前进位加法器的verilog实现。用VHDL语言，附加检验tb.v-Four lookahead adder verilog implementation. VHDL language, additional testing tb.v
4weijianfaqi_verilog
- 四位加法器的verilog实现，用VHDL语言，附tb.v。-Verilog achieve four adder, using VHDL language, with tb.v.
4weizhucijinweijiafaqi_verilog
- 四位逐次进位加法器的verilog实现。附tb.v文件。单片机开发，数字逻辑与处理器基础实验-Four successive carry adder verilog implementation. Tb.v attached file. SCM development, digital logic and processor basic experiment
8weijiafaqi
- 8位加法器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-8 adder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
lab7_adders3
- 加法器的verilog实现，第二种方法：超前进位加法器 -Another implementation of adder in verilog
mixed-language--desvription-of-a-4x4-comparator.z
- mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
CLA4
- Carry look a head adder Verilog
bcdflag
- verilog code bcd adder using flag register
Adder_12bit
- 带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.
book3e
- 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
carrylookaheadadder_4bit
- 4-Bit Carry Look Ahead Adder Verilog Code in Xilinx
half_band
- 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
adder_32bits
- 采用“进位选择加法”技术设计32位加法器 Verilog语言编写-32 bit adder
bcd_adder
- BCD ADDER USING VERILOG