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half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
clock_div
- verilog编写的分频器,基于计数器编写的-divider verilog prepared
fenpin
- 这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写-This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog
FPGA_Divider
- 本源码是用verilog语言编写的FPGA的除法器和74LS138及D触发器模块。-The source code is written in verilog FPGA divider and 74LS138 and D flip-flop modules.
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
xunfachufaqi
- 从原理到实现的循环除法器的Verilog代码-Circular divider from the principle to the implementation of the Verilog code
SDivider16bit_V120
- 循环型除法器Verilog代码，带有8位小数，可使除法器固定长度，缩减时钟开销-Streamlined divider Verilog code, with eight decimal places, make fixed-length divider, reducing the overhead clock
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
clockdiv_teste
- Clock division program write in Verilog with selected divider (32 bits)
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
counter
- 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language
fenpinjishuqi
- 本文档包括实现分频的方法以及奇数分频偶数分频的verilog代码 经测试可用-This document includes methods to achieve divide and even the odd divider divider verilog code used by the test
IntegerDivider
- 整数除法器 无负数复数 期末项目 verilog-integer divider
traffic
- 基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
fp_prj
- 分频器，Verilog语音编写，quartus仿真过，可以利用使蜂鸣器发生-Frequency divider, Verilog speech writing, quartus simulation, can make use of the buzzer
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
freq_div
- //奇数倍分频器基于verilog HDL.-(ODD number)Freq Divider based on Verilog HDL.
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language