搜索资源列表
存储器模型及测试台
- 512x8存储器模型,及其测试台，用verilog写-512x8 memory model, and the tester, using Verilog write
risc8
- 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
memoryverilog
- 一个关于MEMORY设计的原代码,使用VERILOG编写的 希望对大家有些帮助-one of the original Memory design code prepared by the use of verilog we hope to help some
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
- 来自于ALTERA官方网站。 本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。 附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
Verilog-FIFO
- 可综合的Verilog FIFO存储器，可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
memory-controller
- 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
mem_wb
- 采用Verilog编写的存储器，使用lpm_ram_dq模拟主存。主要内容为实现了存储器的奇偶分体，使得该存储器可以进行字或字节的读写操作。-Written by Verilog memory, use lpm_ram_dq simulated main memory. The main content of the memory parity split making the memory word or byte read and write operations.
Verilog
- RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
verilog-FAQ
- Low power SRAMs have become a critical component of many VLSI chips. This is true for microprocessors, where on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and main memory. Simu
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
mem32x1024
- 基于verilog的32*1024的存储器设计-Verilog memory design based on 32* 1024
Verilog-testbench-and-memory-I2C
- verilog编写的测试平台，内含具体project和储存模块的编写-Verilog testbench for digital design Memory I2C module Assignment
verilog
- 用verilog设计的寄存器，储存器，锁存器，译码器以及在其中用到的八位串联并联间的相互转换。-Verilog design registers, memory, lock latch decoder and the use of eight series parallel conversion
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t
AT25160B
- 该代码完成存储器的数据存储和读取功能，该芯片是一款Atmel的SPI接口的EEPROM存储芯片。(The code completes the memory data storage and reading function, the chip is a Atmel SPI interface EEPROM memory chip.)
sdram_ip
- 完成SDRAM的上电配置，状态机编写其读写模块，存储模块，并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
sram_sp_hse_8kx8
- SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)
sram
- FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)