搜索资源列表
FSM_3blocks
- 经典3段式有限状态的verilog HDL描述，在modelsim 中仿真通过。-A classical FSM of three paragrahs, which is described by verilog HDL and simulated in modelsim successfully.
ic2
- 一个IC2的verilog HDL设计，包含了modelsim的工程文件。-This is a IC2 design, which is simulated successfully in modelsim.
cordic_pipelined
- CORDIC算法的流水线verilog HDL实现，包含modelsim仿真所需的设计文件与testbench。-This is an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
LineBuffer
- Verilog HDL的移位寄存器的modelsim仿真
xiaoshu
- 基于Verilog的小数分频,带testbench，可直接modelsim仿真-Verilog-based fractional divider with testbench, modelsim simulation can be directly
div_clk
- verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
fsm_seq_det
- verilog 状态机实现序列检测。简单明了，打开modelsim-change directory -do sim.do 即可-State machine sequence detection.
FIFO
- 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
gaus_filter
- This Gaussian filter is implemented by Verilog HDL and successfully simulated on ModelSim. Besides, it has been implemented on Altera DE2-70 board
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法，采用Modelsim+debussy联合仿真，里面包含一个加法器实例，批处理文件，仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch
Low-Error-and-Hardware-Efficient-Fixed-Width-Mult
- VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and m
booth_multiply
- 布斯乘法器，采用verilog语言实现 经过modelsim仿真-Booth multiplier using verilog language through modelsim simulation
Clock-Divider
- this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
I2C_control
- I2C两线式串行总线的控制端的verilog源代码，经过编译和modelsim仿真后是正确的！-Two-wire I2C serial bus control terminal verilog source code, after compiling and modelsim simulation is correct!
micron-lpddr-sdram-lpddr_model
- modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。