搜索资源列表
chuanbing
- 串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
arm9verilog
- AMBA AHB verilog Source code
RAM
- 单端口RAM，自己写的单端口RAM，同步写入同步读出，包括TESTBENCH和测试模拟文件-RAM
VHDL
- 介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真 ，行为级描述及仿真，延时的特点及说明 介绍Verilog testbench，激励和控制和描述 结果的产生及验证，任务task及函数function 用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
8051vlog
- 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
TestBench_Primer
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
small-programs-using-verilog
- 148个用verilog编写的小程序，易于初学者学习，部分代码还有testbench-148 small programs written using verilog, easy for beginners to learn, there are some code testbench
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help
testbench
- 介绍如何编写verilog的仿真程序，很适合初学者-How to write verilog simulation program, it is suitable for beginners
mppt_mod
- maximum power point tracking system (MPPT) VHDL code with testbench
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Viterbi_Verilog
- viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
ssram-and-tesebench
- 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware descr iption language Verilog ,and include the testbench.
Writing-Testbenches-using-System-Verilog
- writing testbench in system verilog
how-to-write-testbench
- 怎样写testbench ， 仿真， modelsim， system verilog or verilog， 代码风格，行为级代码-how write testbench，do simulation, modelsim, system verilog or verilog , behaveral level code