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jtdvhdl
- 自己做的VHDL交通灯控制器；分频器、信号控制器、时钟模块；EDA； 通过了仿真、运行。时间可以设置为随意的两位数.-code and jpf
pid
- This includes a PID Controller and a PWN Generator for implementation on an FPGA using VHDL
EP1C3_12_5_RSV
- 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
vliw
- vliw processor core vhdl files compiled by myself partly and through the help of net resources.
hdlc
- hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
sram_060803
- SRAM的读写代码，对SRAM进行了乒乓操作，用VHDL语言进行设计，很有参考价值，甚至可以直接复制代码来进行自己的设计-SRAM read and write code, ping-pong operation carried out on the SRAM, using VHDL language design, of great reference value, or even directly copy the code to carry out their own designs
SDR-SDRAM-ctl1
- SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
sdramvhdl
- SDRAM存储器芯片，FPGA的接口控制，VHDL语言编写-SDRAM memory chips, FPGA interface control, VHDL language
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
music
- 出血FPGA,用VHDL做的音乐盒，请各位大侠指点。-Bleeding FPGA, using VHDL to do a music box, please instruct heroes.
count10
- 用vhdl编写的十进制计数器，内部说明详细。-Prepared using VHDL decimal counter, the internal descr iption in detail.
soldervhdl
- 自动售货机的vhdl程序 在quartus环境下编译运行通过-Vhdl program for vending machine
CPU
- quartus7.2下以VHDL编程，分为多个模块，在链接原理图中编译。-quartus7.2 next to VHDL programming is divided into multiple modules, compile the schematic in the link.
turbo_VHDL
- Turbo码的VHDL描述，可以下载下来-VHDL descr iption of Turbo Codes
zy
- 这是一个vhdl的例子 ，可以实现密码锁-This is a VHDL example, you can achieve it locks work
vga
- vga显示时序控制，vhdl产生所必需的时序-vga display timing
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
flash_memory
- VHDL model for a NOR Flash
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
fpga
- VHDL写的fpga程序，可产生三角波，方波据此波，正弦波，可实现任意频偏的调频，调相，调幅-Fpga write VHDL program can generate triangle wave, square wave accordingly wave, sine wave, can achieve any frequency offset of the FM, PM, AM