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VGA_change
- 程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例，源文件保存在src目录，QII的工程文件保存在Proj目录。-Program can display in VGA resolution display to 800x600 square sample and letters examples, source files stored in the src directory, QII the project file stored in the directory Proj
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器，DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
DE2Project_restored
- 一个在全国电子设计大赛上的基于DE II的实际工程-One in the National Electronic Design Competition on the DE II Based on the actual project
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
Multi11Mulply
- 本程序是11位带符号位的乘法器，其中最高位为符号位(sign)，中间7位是指数部分(Exponent)，最后3位是尾数(Matissa)。表示数据的范围是-2^-63-----+2^64.该工程文件有完整的程序，以及波形,验证正确。-This procedure is the unsigned 11-bit multiplier, one of the highest for the sign bit (sign), are between 7 part Index (Exponent), th
TopLevel_DualPort_Ram_XilinxCore
- Top Level Dual Port Ram Core Project, VHDL code
PWM_control_motor
- This a project about PWM. Application in motor speed control-This is a project about PWM. Application in motor speed control
project1_report1
- The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second lev
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
FreeDCT-L
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct-thesis
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
dct2
- Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
project
- synthesizable code for shift register of user defined size
High_Speed_Stream_ADC
- This project attempts to stream high-speed ADC (or other digital) samples into a computer equipped with USB 2.0 CY3681FX2 AD9245
aes_crypto_core_latest.tar
- Consecutive AES core Descr iption of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
crc
- CRC校验码的实现，校验码6位，寄存器串行实现方式，经项目实际验证正确-CRC Check Code realization Check 6, register serial ways, the right to verify the actual project