搜索资源列表
Xilinx
- vivado 14.2 crack,can be used -vivado 14.2 crack
ug947-vivado-partial-reconfiguration-tutorial(1).
- tcl partial reconfig synthesis code
bit2dec_fft
- bit to dec 并对数据进行FFT变换，配合xilinx Vivado采数使用。-and the data bit to dec FFT transform, with the number of use xilinx Vivado mining.
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
hdl-master
- AD9361的ip核，已经调试通过，在vivado上可以运行通。AD9361是一个双通道的便捷收发器，通常用于3G/4G基站。-AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base stations.
xapp1082-zynq-eth
- PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC 是学习Vivado 入门文档，源自xilinx，权威易懂 -PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 AP SoC Learning Vivado entr
yuv422tobt1120
- yuv422转bt1120时序，vivado工程，用tpg做信号源-yuv422 to bt1120
verilog
- vivado的led灯的学习程序，有兴趣学习soc的可以下载-the program for vivado study on SOC
EqualizeHist_hls
- 灰度图象直方图均衡化。使用vivado的HLS来实现直方图的均衡化。-Gray image histogram equalization. Use vivado of HLS to achieve histogram equalization.
sobel
- 基于FPGA的sobel滤波。使用vivado 2014.2实现的YUV图像的sobel滤波。-Sobel filter based on FPGA. YUV image Sobel filtering using vivado to achieve the 2014.2.
tb_axi4
- 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序，有助于学习vivado和fpga-verilog vivado xilinx
zybo_zynq_audio
- Zybo xc7z010 uation board,ssm6203音频编码器，PC端给音频输入，HPH输出口输出过滤噪音的音频，软件：xilinx vivado, vivado HLS, SDK-Zybo xc7z010 uation board, ssm6203 audio encoder, PC end to the audio input, HPH output port noise filter audio software: xilinx vivado, vivado HLS, SD
Vivado_Zynq_Guide
- Vivado的简明教程及Zynq的开发流程-Vivado concise tutorials and Zynq development process
hdl-master
- ADI ad9361 vivado 下源代码-ADI ad9361 vivado source code
sin_wave
- 在vivado开发环境下，调用ram IP，实现可调频的正弦波信号发生器。-vivado IP signal generator
adder8
- 8位加法器源代码，vivado实现编写。-8 adder Source, vivado achieve write.
Vivado_debug_to_MATLAB_doc
- 介绍了Xilinx Vivado debug调试环境下，将调试数据导入MATLAB的方法，简单易用，欢迎交流-Guide for Xilinx Vivado debug, import data to matlab.
ug871_vivad_HLS_tutorial
- Xilinx Vivado HLS 高层次综合工具的软件使用说明-Vivado HLS Xilinx high level integrated tool for the use of software instructions
21ic_VIVADO-verilog
- vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA -vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA v