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PingPang_buffer_20160526
- 源码仿真 乒乓 缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation ping-pong cache data stream transmission, the file containing the simulation test, vivado project.
LED
- 基于VHDL语言，利用Vivado开发的16位跑马灯-A 16-running-lights program based VHDL which is developed by vivado
firtest2015.2
- vivado fir 测试工程,dds chansheng shuju ranhou gei fir -vivado fir
mdio
- 用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件-Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file
vivado2016.2-license
- Vivado Design Suite v2016.2版本license-the license of Vivado Design Suite v2016.2
fir_vivado
- 此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现-in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari
cos_test
- 该段代码是产生正弦信号的一个测试代码，能够基于vivado这个平台产生正弦信号-this code is the generation of the signal of sin base on the platform of vivado
Dac_spi
- spi dac for artix7 vivado
rna
- top transmition of implement spi, compiled in vivado 2016 in basys 3
QAM
- 16QAM调制 基于vivado环境下16QAM调制 -16QAM modulation
VivadoLicense
- Vivado liscenses for the software
Vivado-License
- vivado2014.2的license-vivado2014.2' s license
vivado_jian_ming_jiao_cheng_
- Vivado中文使用教程,详细介绍了XILIN开发工具vivado的使用方法.-Vivado Chinese design manual
shifter8
- c语言实现移位寄存器 可以形成数据流 在FPGA中实现硬件描述语言 含有vivado实现-C language shift register can form a data flow in the FPGA hardware descr iption language contains vivado implementation
sdram_test
- 在vivado中用于测试SDRAM，DDR3学习比较有帮助-the testbench for ddr3
xilinx_ise_vivado_2017
- vivado最新可用license2017-vivado license ok for 2017
Filter_Convolution_Example
- Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx-Example of a convolution filter implemented in Vivado HLS, the high level synthesis tool Xilinx
uartlite_double
- 基于ZYNQ开发平台VIVADO开发环境调用PL双UART_LITE源程序-Based on the ZYNQ development platform VIVADO development environment Call PL double UART_LITE source
ex_2
- FPGA 代码,可以作为练习VIVADO的使用于学习- CS_r[0] < CS CS_r[1] < CS_r[0] wrreq_r[0] < wrreq wrreq_r[1] < wrreq_r[0] READ_sig_old[0] < READ_sig READ_sig_old[1] < READ_sig_ol
conv
- Conv Encoder for VHDL Vivado