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61EDA_C2714
- xilinx ISE 4.1的入门，简单简单的。看看看看！-xilinx ISE 4.1, entry, simple simple. Look look!
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
adder
- adder in vhdl , ff , using xilinx ise -adder in vhdl , ff , using xilinx ise
lab_manual_tutorial
- 用赛灵思ISE9.2和Spartan-3E设计的四位计数器-4- Bit Counter with Xilinx ISE 9.2 and Spartan 3E
Lab01
- 快速熟悉ISE软件的使用，适合初学者，是一系列小操作流程的集合。-To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circuits To become familiar with
ISE_lab15
- 采用xilinx公司的ise软件实现电子钟-xilinx ise
ISE_trafficlight
- 采用xilinx 的ise 软件实现交通灯的功能，要用就要先安装ise哈-xilinx ise
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
SPconversion_CPLD_FPGA_VHDL
- 基于状态机的8bit并串变换，使用VHDL语言，使用Xilinx ISE，程序特点是使用了状态机，通过分析可以学习如何使用状态机编程，并完成8bit并串变换的功能-8bit based on state machines and string transformation, using VHDL language, using the Xilinx ISE, process characterized by the use of the state machine, the analysis c
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Example-1-1
- XILINX ISE 9.X FPGA/CPLD设计指南第一章代码-XILINX ISE 9.X FPGA/CPLD Design Guide Chapter code
cangyongEDAgjzn
- 4.1 Altera MAX+plusⅡ操作指南 4.1.1 MAX+plusⅡ10.2的安装 4.1.2 MAX+plusⅡ开发系统设计入门 4.2 Xilinx ISE Series的使用 4.2.1 ISE的安装 4.2.2 ISE工程设计流程 4.2.3 VHDL设计操作指南 4.2.4 ISE综合使用实例 4.3 Lattice ispDesignEXPERT的使用 4.3.1 ispDesignEXPERT的安装 4.3.2 原理图输入方式设计
music
- 蜂鸣器实现播放音乐，两个按键可选择播放，共三首音乐可选。Xilinx ISE 9.1环境下工程。-Buzzer for playing music, playing the two keys to select a total of three songs optional. Xilinx ISE 9.1 environment projects.
ADPCMEncoder
- ADPCM encoder with ICON, VIO, ILA, working on Xilinx ISE and chipscope.
ADPCMDecoder
- ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
perjoko_ting_ting
- Simple Microprocessor built with XILINX ISE
XilinxFPGAISEDSPDESIGN(1-60)
- 系统讲述了XilinxFPGA的开发知识,包括FPGA开发简介、VerilogHDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISE开发环境使用指南、FPGA配置-System, the development of knowledge about XilinxFPGA, including the FPGA development profile, VerilogHDL language based on chip-based Xilinx HDL Language Advanced
VHDL_simple_settable_clock
- 基于Xilinx ISE软件的用VHDL编写的一个简易的可调节时钟，具有时、分、秒功能-Xilinx ISE based,a simple settable clock using VHDL, with hours, minutes, seconds functions