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16bit-CLA
- 16 bit carry look ahead adder verilog code
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
adder
- 高达16位加法器的实现,工作环境在ISE,modesim,该例程较为详细!-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Adder
- 实现十六位加法器,是书籍上配套的应该可用-This is an 16 bit adder using vhdl
adder17
- 实现17位加法,利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器,并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
16weijiafaqi
- 本程序是在一位全加器的基础上设计一个16位的加法器,用Verilog HDL语言描述.-This procedure is a full-adder based on the design of a 16-bit adder, using Verilog HDL language to describe.
ADDER
- simple 16-bit CSA Adder
RippleCarryAdder
- Ripple Carry Adder in Vhdl
adder
- 8位cla,采用for结构,可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
adder16b
- 潘松那本书上用vhdl语言描述的16位并入并处加法器-Pan book vhdl language used to describe the 16-bit adder into his
flowvhdl
- 16 bit adder source code.
wallace
- wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
adder3
- 此源代码是基于Verilog语言的七人投票表决器 、2 个 8 位数相乘 、8 位二进制数的乘法 、同一循环的不同实现方式、使用了`include 语句的 16 位加法器 、条件编译、加法计数器中的进程、任务、测试、函数、用函数和 case语句描述的编码器、阶乘运算函数、测试程序 、顺序执行、并行执行,特别是七人投票表决器,这是我目前发现的最优的用硬件描述的源代码。-The Verilog language source code is based on the seven-vote, and
cla16
- 16位超前进位加法器的源代码,整个工程文件都有,是在ISE10.1下建立的,可以帮助理解超前进位原理(对了,是Verilog的,因为上面没看到只好选VHDL了)-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Ver
16-bit-adder
- 这是关于16位加法器的实现代码及仿真图形的压缩文档-This is about 16-bit adder implementation code and simulation graphics archive
adder
- It is VHDL code of 16 bit adder program, counter and IIR filter
16-bit-binary-full-adder
- 16位二进制全加器,带最高位的进位,主要用QUARTUS仿真工具实现-16-bit binary full adder
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器,16位,基于verilog HDL语言(16-bit carry-skip adder)
16-Bit_RCA
- 16 bit Ripple Carry Adder using vhdl on modelsim