搜索资源列表
ddr_verilog_xilinx
- DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
DDR_SDRAM_verilog
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的
ddr_sdr
- DDR SDRAM 控制器 包含测试向量和仿真模型-DDR SDRAM control
DATA-PATH.vhd
- signal data for ddr sdram
sdram_vhdl
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
SDRAM_DDR_DDR-II_Rambus_DRAM
- 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM)-The principle and the timing of the memory (SDRAM, DDR, DDR-II, Rambus_DRAM)
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
MT46H32M16LF
- Mobile DDR SDRAM MT46H32M16LF – 8 Meg x 16 x 4 banks MT46H16M32LF/LG – 4 Meg x 32 x 4 banks
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
sdram
- SDRAM 接口程序，里面涵盖 datasheet，原理容易懂，对学习ddr有兴趣的可以下来看看。-SDRAM interface program, which covers the datasheet, easy to understand the principle of learning ddr can look down.
DDRSDRAM_
- 基于FPGA 的DDR SDRAM 的重要资料 内附代码-FPGA-based DDR SDRAM code containing important information
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
sdram
- 基于ARM 的S3C6410 DDR内存的驱动，实现了内存的初始化等-The driver of DDR
ddr_sdram
- this document explain de function of ddr sdram controller
atmel-sdramc
- Atmel (Multi-port DDR-)SDRAM Controller driver.
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
DDR2_SDRAM操作时序
- DDR2_SDRAM操作时序，介绍的很详细，不错(DDR2? SDRAM operation sequence, very detailed introduction, very good)