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fifo
- fifo 即实现数据的先进先出,是用verilog编写的 就撒开了几分-fifo hjahfjhsjeikkdnakfnakjfakjkf
VHDLFIFO
- 用Verilog 写一个8x16 的FIFO,完成先入先出的功能,并且在FIFO读空时输出EMPTY 有效信号,读指针RP 不再移动;FIFO 写满时输出FULL 有效信号,并且即使WR 有效也 不再向存储单元中写入数据(写指针WP 不再移动)。 -NO
Chapter-9
- Verilog编写的异步串行FIFO程序,包括各种标志位,指针注释,其中还有SDRAM的读写程序-Asynchronous serial FIFO write Verilog procedures, including a variety of flag, pointer annotations, among them a SDRAM read and write procedures for
ASY_FIFO
- 用Verilog编写的异步FIFO,可以方便的实现同步异步的转换,在全局异步局部异步的系统中得到广泛应用-ASY_FIFO written with verilog,and it is very useful in a GALS system
afifo
- verilog编写的异步FIFO代码,功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
fifo_syn
- 本源码是用VERILOG实现FIFO的读取,并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
Verilog_USB_OUT
- USB out,使用Verilog写的,包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document,USB firmware
sdfsdFifo
- 这是一个异步fifo的Verilog 代码,该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
fifo_verilog
- 用verilog 实现 fifo,宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs
asy_fifo
- 用verilog实现异步fifo,通过仿真-Asynchronous with verilog fifo, the simulation
fifo
- 采用verilog HDL语言实现FIFO的功能,内涵测试程序,有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
FIFO
- 此程序为verilog语言,实现的功能为FIFO功能,包括三个部分,分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
my_FIFO
- FIFO的verilog实现,成功通过验证,很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
rx_fifo
- verilog语言写的接收机FIFO,适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
FIFO
- verilog 实现FIFO存储功能,八位数据宽度,16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Verilog-FIFO
- 可综合的Verilog FIFO存储器,可以实现先如先出的设计-Synthesizable Verilog FIFO memory can be as-first-out design
FIFOED_UART
- CAL_UART核verilog源码,带FIFO,FIFO深度可设置。-fifoed uart ip core. cal_uart.
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计,其中写时钟100MHz,读时钟为5MHz,其中RAM的深度为256。当写时钟脉冲上升沿到来时,判断写信号是有效,则写一个八位数据到RAM中;当读时钟脉冲上升沿到来时,判断读信号是有效,则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志,不能再往RAM再写数据;当RAM中数据读空时产生一个空标志,不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
Asynchronous-FIFO-Design
- 异步FIFO设计,一共包含6个模块,使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
uart_1203_4
- MUC+fpga 串口扩展,已调试通过,4路串口共用中断,收发fifo,波特率可调,其他的可以自己添加,网上类似资料极少,极具参考价值!只提供verilog源码!-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o