搜索资源列表
Buf_FiFo
- verilog 编写的FIFO,里边有IP核和控制模块,-verilog write FIFO, inside the IP core and control module,
VerilogBasicICDesign
- Verilog基本电路设计,包括时钟域同步、无缝切换、 异步FIFO、去抖滤波-Verilog basic circuit design, including clock domain synchronization, seamless switching, asynchronous FIFO, debounce filter
async_fifo
- system verilog environment for asynchornous FIFO
uartfifo
- 串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。-uart communication
arinc429_transmitter
- Simple Arinc-429 transmitter channel descr iption on Verilog HDL with parameterized DATA FIFO.
apb_spi
- Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
async_fifo
- 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。(不能直接使用。)-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)
parameter_uart_rx
- 串口接收模块,可以通过parameter,参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数,并根据缓冲的大小配置FIFO就可以使用。对帧错误(停止位不为高),检验错误和读FIFO超时(FIFO满的情况下,有新的数据到)等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
oscillo_1
- 简单数字示波器的verilog设计,涉及到时钟同步,FIFO的配置和使用,非常适合用来学习FPGA以及熟悉quartus II 软件。(digital oscilloscope design)
uart_design
- UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)