搜索资源列表
fir_PGA
- 一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
FIR_matlab_verilog
- matlab 仿真低通滤波器，然后用verilog硬件实现-using matlab to simulate a fir lowpass, then using verilog to implement it.
FIR_chanbing
- FIR滤波器的verilog HDL语言编写的，希望对大家有用-FIR filter verilog HDL languages, we hope to be useful
fir
- FIR滤波器，使用Verilog硬件描述语言进行编程-FIR filter, using the Verilog hardware descr iption language programming
FIR_Filter
- verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
fir_lms
- finite impulse response LMS algorithm verilog code
Digital-Signal-Processing-with-FPGA
- FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
fir-filter
- fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
DA_FIR_VERILOG
- 基于DA算法的FIR滤波器的verilog实现-DA-based FIR filter algorithm to achieve the verilog
fir-filter
- 11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理-11 order of fir digital filter verilog programming, linear phase, the coefficient quantization
FIR
- 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
verilog-fir
- 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
CIC_fir-Verilog
- 本程序是一个CIC滤波器设计，有助于初学者对滤波器设计设计有一个初步的了解-CIC fir
FIR
- 一个不错的数字滤波器verilog源码，希望大家能用的上-A good digital filter verilog source
fir
- 16阶的FIR滤波器的verilog文件，包含了测试报告。-16 order FIR filter verilog file contains a test report.
fir
- 用Verilog语言设计的一个数字FIR低通滤波器，很实用，通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
fir
- 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
FIR
- 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
FIR
- 使用Verilog语言编写的FIR滤波器,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog