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20080931
- Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol
CAN_I2C_USB_yuanma
- CAN总线，I2C，USB等的FPGA实现源码，可以利用原有代码，快速开发出自己的代码，物有所值-CAN bus, I2C, USB, etc. FPGA implementation source code, we can use the original code, and to quickly develop its own code, value for money
FPGA2SRAM
- verilog code that can implemented on ACEX1k FPGA for a SRAM-verilog code that can implemented on ACEX1k FPGA for a SRAM
sdr_verilog
- 用Verilog实现SDR_SDRAM的控制器,可用FPGA实现对普通SDRAM的读写操作!-SDR_SDRAM using Verilog implementation of the controller, the FPGA can be used to achieve the ordinary SDRAM read and write operations!
burstpage
- SDRAM控制器在FPGA实现源代码，能实现burst传输-SDRAM controller in FPGA realization of the source code, can achieve burst transfer
fpgaConfig_V1_2_SFLASH_20090507a
- 自己写的一个使用单片机配置FPGA的下位机C代码，使用一个C8051F330,外置SPI FLASH,通过串口可将程序写入FLASH,上电时自动加载到FPGA完成配置。-Wrote it myself, using a microcontroller to configure FPGA code for the next bit plane C, using a C8051F330, external SPI FLASH, the program is written through the s
ISD1700
- ISD1700模块程序，有做的可以看看，挺好的。-ISD1700 module procedures, you can do look quite good.
video_board_schemtic1
- this the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connect to a DE1 FPGA board or any other you fancy-this is the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connec
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
TCPIPGuide_2-0_s9
- WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and t
fpganaoz
- 基于FPGA闹钟系统的设计。 1.秒模块实际上是一个计数器，一秒记录一次并输出。 2.分，时模块在一个脉冲上升沿计数一次的基础上，加入了时间调整控制。 3.调整时间的控制模块，在使能信号有效时，才可实现时分的调整。 4.闹钟调整及控制模块，可实现闹钟设时的调节功能。 5.显示模块，实现时间与闹钟显示的切换。 6.闹铃模块，实现闹铃的发声装置。 7.总逻辑模块，实现电子闹钟相应功能的总系统。 -FPGA-based alarm system design. 1. S
am29lv160
- nor flash的源码，可以做为启动代码烧写的代码-nor flash source code, can be used as boot code Shaoxie code
oscillograph
- 用VHDL编写的oscillograph数字部分源代码，在Altera FPGA上跑通。直接把模拟部分输入输出AD，DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this modul
VHDL_Data
- 潘松的VHDL使用教程，已经制作书签，阅读方便，是学习VHDL新手的必备资料，FPGA/CPLD开发者可以参考的资料，-Pinson use of VHDL tutorial have produced bookmarks, reading easy to learn the essential information on VHDL novice, FPGA/CPLD developers can refer to the information,
DS18B20_VHDL
- DS18B20 VHDL 配置程序，fpga 验证，可以实现配置-DS18B20 VHDL configuration program, fpga verification, configuration can be achieved
i2c_master_model
- i2c仿真model,可用于整体的FPGA仿真系统,用于i2c slave 设计的正确验证-i2c simulation model, the FPGA can be used for the whole simulation system designed for the proper verification i2c slave
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
counter
- 基于VHDL的计数代码，可用于FPGA芯片对步进电机的控制-Count based on VHDL code for FPGA chips can be used to control stepper motor
tta
- 基于移动触发结构设计的可配置专用处理器的实现。-Trigger structural design based on mobile-specific processor can be configured to achieve.
eda
- 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the desi