搜索资源列表
Xilinx_FPGA
- 介绍了FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE-Introduced the entire FPGA design process: Modelsim>> Synplify.Pro>> ISE
The_entire_FPGA_design_flow_Modelsim_Synplify.Pro_
- 详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed descr iption of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
FPGA_design_process
- FPGA 设计全流程：Modelsim>>Synplify.Pro>>ISE-FPGA design of the whole process: Modelsim>>Synplify.Pro>>ISE
mc8051_top
- 利用synplify8.1综合的8051IPcore电路图，可用synplify打开查看电路-8051 RTL Schematic
synplify_for_xilinx
- 英文资料，综合工具synplify 对xilinx的支持。英文不错的进-Information in English, integrated tools synplify on xilinx support. Good progress in English
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
FPGAdesignandFIRimplementation
- 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
synplify_pro-text
- 介绍了synplify pro的使用方法，好不容易找到的，欢迎下载，希望与大家共享。-introuducing the text of synplify pro,it is fit for learning the application of the soft
synplify_pro-tutorial
- 做fpga综合的文档，如果你在做 肯定会用到-synplify tutorial
OneD_DCT8
- 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled scr ipt
FPGA
- fpga综合工具比较，三种综合工具，包括synplify，dc等-fpga synthesis tool compared with three integrated tools, including synplify, dc
verilogSerialcommunication
- FPGA实现RS-232串口收发的仿真过程（Quartus+Synplify+ModelSim）-On the RS-232 online asynchronous transceiver introduced a lot, recently there groping to do with the ModelSim timing simulation, combined with the online reference and their own thinking, do this thin
Example-b8-6
- Synplify Pro综合流程序仿真，注：本范例同时提供Verilog和VHDL两种语言版本，请读者根据习惯选用不同的源代码进行操作。-Synplify Pro comprehensive process simulation (note: this example provides two Verilog and VHDL language version at the same time, please choose the different readers according to t
Prescaler-to-use-VHDL-design
- 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, i
Example-b8-6
- Synplify Pro综合流程，体会Synplify Pro综合工具的使用方法与技-Synplify Pro synthesis process, and technology usage experience of Synplify Pro synthesis tool
Example-s5-1
- “\Example-s5-1\des” 目录下为设计工程，其设计输入采用Synplify预先编译好的.vqm网表 “\Example-s5-1\source”目录下为设计的源代码，这里只给出了Verilog语言实例，仅供读者参考 “\Example-s5-1\source \area_opt”目录下为面积优化的代码 “\Example-s5-1\source \perf_opt”目录下为性能优化的代码 “\Examp
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
ChannelizerFFT
- FFT 模型，能够演示多通道FFT的实现过程。-FFT Multi-channel model. This simulink model can generate RTL code via Synplify DSP.