搜索资源列表
FPGA_DDS
- 基于Cyclone EP1C6240C8 的AD9854 DDS的接口程序，使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。 通过FPGA口线模拟AD9854的控制时序。 提供DDS信号波形变换、DDS频率调整、DDS内部比较器使用等功能。-Cyclone EP1C6240C8 of the AD9854 DDS-based interface program, use the FPGA to control the DDS signal generation, so a
interface
- 采用Cyclone EP1C3，VHDL程序算法实现了信号波形的实时采样并回放，同时能测量时域信号的频率，通过与MCU的8位并行接口，进行相互通信。-Using Cyclone EP1C3, VHDL program algorithm of the signal waveform of real-time sampling and playback at the same time capable of measuring the frequency of the signal in time
pisca
- machine with 16 possible states flip flop desmultiplexor language VHDL with fpga cyclone 3
Millington_GamePhysics_cd
- Millington game engine cyclone
LCDfcout
- FPGA实现LCD显示的频率计，芯片为cyclone-FPGA realization of the frequency meter LCD display chip for the cycloneII
CycloneIII
- 有关FPGA的AS、JTAG配置的中文资料-The FPGA-AS, JTAG configuration of the Chinese data
radar1
- 介绍了利用Altera公司的FPGA 器件 (cyclone) 产生线性调频信号的DDS工作原理、设计方案、电路结构。并详细讨论了利用FPGA 器件实现DDS技术时, 采取的一些改进优化措施-Introduced the use of Altera' s FPGA device (cyclone) generate a linear FM signal DDS working principle, design, circuit configuration. And discussed i
LAB_ATTEMPT2
- Verilog and SOPC implementation of interrupts for DE2 board and Cyclone -Verilog and SOPC implementation of interrupts for DE2 board and Cyclone II
ezxfba
- motorola ezx 平台下的fba模拟器,仿照 Cyclone ，用 ARM 汇编重写了 MAME 的 NEC V20/V30/V33 CPU模拟核心,基本可以全速模拟hook（铁钩船长）了-motorola ezx platform of the fba simulator, modeled on Cyclone, rewritten MAME compiled with ARM' s NEC V20/V30/V33 CPU simulation core can be basic
YYPP
- 计算机组织与系统结构实验 用一个74182芯片和四个74181芯片构成一个4位逻辑算数运算器，实现平台为Cyclone II EP2C35F672C6-Computer Organization and Architecture Designing for Performance Experiment
DE2_70_TOP
- 在quartus上实现电子锁的设计，采用cyclone的板子，方便设置初始密码，更新密码-Quartus to achieve in the design of electronic locks, using cyclone of the board, easy to set the initial password, update password
cycloneIII_3c120_dev_niosII_standard
- 该源码是关于FPGA片上系统sopc的nios处理器设计，他实现了led，lcd以及Internet网络各种功能，源码已经测试通过，读者可以使用-The source is on the FPGA chip on the system sopc the nios processor design, he realized the led, lcd, and Internet networking features, source code has been tested, the reader
exercicio4
- VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone -VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone II
HexatoSSD
- VHDL program. It s a converter from Hex to SSD format using Cyclone -VHDL program. It s a converter from Hex to SSD format using Cyclone II
TrafficLightController
- It s a vhdl program. Simulates a traffic light controllet using a Cyclone II FPGA
UserDefinedFunction
- It s a VHDL program. The program does a generic gray. Using a Cyclone II FPGA Board.
async_uart
- 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
DE2_TV
- 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
NAT
- 乐器数字接口MIDI（Musical Instrument Digital Interface），是数字音乐的国际标准。任何电子乐器，只要能处理MIDI消息，并有合适的硬件接口，都可视为一个MIDI设备。本设计完成一个MIDI音乐播放器，该设备以MIDI技术为基础，在Altera公司Cyclone系列FPGA EP1C6Q240C8上实现数字音频合成。MIDI信号源由PC机串口配合串口MI-dssssdsfddsds