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DDRSDRAM_MT46V32M16TG
- ddr控制器 对DDR实现读写控制-ddr control
DDR
- HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Magnetic
- 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰，还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号，像一些RF电路，PLL，振荡电路，含超高频存储器电路（DDR SDRAM，RAMBUS等）都需要在电源输入部分加磁珠，而电感是一种蓄能元件，用在LC振荡电路，中低频的滤波电路等，其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line frequency noise and interfere
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
ddr
- DM6446 ddr ccs 仿真器测试程序-DM6446 ddr program in CCS
DX-PHY
- ddr phy design spec and example-ddr phy design spec and example!!
sdram_controller_latest.tar
- sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is me
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
DDRSDRAMconclude
- DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some ref
XAPP200_ddr_sdram_64b
- Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
ddr
- DDR solution for problem in NPC contest
ddr_100Mhz_2011.03.12
- 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the t
DDR-failure-analysis
- DDR failure analysis
DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to ach
DDR
- 关于DDR布线规范，用于指导PCB布线.-Wiring on the DDR specification, PCB layout for
emb-dev-c3-appsel
- vhdl code for altera ddr design
TEST-BENCH.vhd
- test bench for ddr 1
tests
- 6437开发板测试程序,RAM,DDR,LED,RTC,USB,VIDEO,SPIROM-DM6437 DEMO program
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl