搜索资源列表
shishi
- 基于FPGA的实时采样系统设计!双口ram典型应用!-FPGA-based real-time sampling system!
equivalent_sample
- 基于FPGA的等效采样系统设计,包含状态机设计,双口ram使用方法,分频设计等-FPGA-based equivalent sampling system design, including the state machine design, dual-port ram usage, frequency design
ram
- FPGA实现可读可写的256字节的ram。-FPGA Implementation of read-write 256 bytes of ram.
dppramm
- 基于fpga的双口ram的设计与实现,好东西,希望大家喜欢-The dual-port ram fpga based design and implementation of good things, hope you like
how_to_use_RAM
- actel的fpga ram核使用手册,想入手学习ram的同学可以参考一下。-the techManual of actel fpga ram ipcore,and the beginner can use it easily.
ram
- 基于FPGA的rom程序(verilog)-rom procedure
ug_ram_rom
- ALTERA公司的FPGA中RAM,ROM的使用手册和帮助-ALTERA' s FPGA RAM, ROM user manual and help
dw8051-used-in-FPGA
- 自己下载的dw8051核,并在atlys fpga开发板上运行成功。其中rom和ram都已经生成,4个并行I/O口也有。编程语言是verilog。另外,还有hex转in文件的小软件,以及Uedit这个文本编辑器,它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four par
dual ram
- 此文件是FPGA工程文件,包含了dualram的设计代码和testbench代码,使用了verilog hdl编写,仿真结果符合设计要求。
ram
- CPU中一个部件——RAM的编程,运用FPGA,硬件描述语言-CPU a part-- RAM programming, using FPGA, hardware descr iption language
Flash-Memory-RAM
- 周立功Fusion StartKit,fpga开发板的实验例程,Flash Memory初始化RAM实验-ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments
RAM
- altera FPGA上的RAM源码 单端口结构 -the RAM the source single port structure altera FPGA
ramIPcore
- 基于quartusII的ram调用,利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
ram
- 练习调用双口ram,fpga自产生65536个递增数,6.25Hz输出,在20ms内读出。-Exercises called dual port ram, fpga increasing number of self-produced 65536, 6.25Hz output within 20ms readout.
vga-with-double-port-ram
- fpga 读写双端口ram并使用VGA进行显示,基于de2-115-vga with read and write double port ram
RAM
- 通过使用fpga,verilog语言来实现RAM的读写功能。-for ram reading and writing
Dual-port-RAM-data-acquisition
- 利用传统方法设计的高速数据采集系统由于集成度低、电路复杂,高速运行电路干扰大,电路可靠性低,难以满足高速数据采集工作的要求。应用FPGA可以把数据采集电路中的数据缓存、控制时序逻辑、地址译码、总线接口等电路全部集成进一片芯片中,高集成性增强了系统的稳定性,为高速数据采集提供了理想的解决方案。-Using traditional methods of high-speed data acquisition system design due to low integration, circuit
Dual-RAM
- DSP EMIF双口RAM和FPGA实现高速通信-DSP EMIF dual-port RAM and FPGA to achieve high-speed communications
基于FPGA的乒乓RAM
- 控制读写乒乓RAMip核代码,通过控制FPGA内部RAM的的读写地址来控制RAM的读写
ram
- 此代码可以是FPGA内部ram存储器在读取一系列数据后,然后每间隔1秒钟读出来。-This code can be read in the FPGA internal ram memory after a series of data, and then read out at intervals of 1 second.