搜索资源列表
testgray
- 有限状态机FSM编程设计及测试，代码合一了，以三位gray码为例，在modulesim5.7上测试通过。-Finite state machine FSM programming design and test, code-one, and with three gray code, for example, in the modulesim5.7 on the test.
topsequence
- modeling of fsm in vhdl
youxianzhuangtaiji
- 有限状态机的说明以及源代码 有限状态机的说明以及源代码-FSM
state_mm
- 有限状态机源码，verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation.
FSM
- finite state machine design
fsm_tb
- An odd parity checker as an FSM using VHDL
johnson_encoding_angle
- An FSM using VHDL and Johnson state encoding for states
CM12864
- cm12864液晶显示器的vhdl驱动代码，基于状态机的转换，实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
FSM
- 这是用verilog硬件描述语言编的moore状态机代码-It is compiled verilog hardware descr iption language moore state machine code
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
FSM
- it explains how to write the statemachins
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
Sequencedetector
- Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
fsm
- 检测输入数据中的“10110”序列，并记录检测到的序列的数目，当序列数目大于3时溢出。 输入信号：iclk //输入时钟 rst_ //复位信号 din //输入串行数据 输出信号：[1:0] catch //检测到的序列的数目 overflow //数目大于3 ，溢出 置高-finite states machine
ser_test
- 用Moore状态机测试序列1110010-Test the series"1110010" in Moore FSM
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
FSM
- Ebended System for finite state machines-Ebended System for finite state machines
Stepper_motor_fsm
- stepper motor fsm is the fsm for stepper motor. It indicates the states of stepper motor.
iiscode
- 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and syn
nuevolcd
- LCD 2x16 Spartan 3E, Controlador based in FSM