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PLL_PLV
- 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示,简单锁相回路[3,4]是由三个电路构成,分别为相位侦测器(Phase Detector)、回路滤波器(Loop Filter)、压控荡器(VCO)-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
C51-phasic-detector
- C51 实现的相位检测,带PROTEUS仿真-C51 implementation phase detection, with PROTEUS simulation
costas的verilog程序
- costas的verilog程序,包含乘法器,DDS,鉴相器,环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Verilog_module
- Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
dpll
- 基于Verilog的数字锁相环。包括三个模块,数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
PhaseBasedTemplateMatching
- Phase Based Template Matching: Phase information is used for matching the input imagery with the template. Both the images are filtered with canny edge detector. The timing efficiency is introduced by implementing skipping steps while doing correlati
9700F
- protel99图 电机相位检测板应用于电机的转速检测和相位检测-Figure protel99 board phase detector used in electric motor speed detection and phase detection
chA
- phase frequency detector verilog
matlabxueqi
- 小学期的源程序 1.试编MATLAB程序。信号 sinc(10*t),-2<=t<=2 m(t)= 0,其它 用100hz的载波来产DSB信号并解调。完成下列工作: 画出已调信号; 求已调信号的频谱,并用图像表示。 画出解调信号; 求解调信号的频谱,并用图像表示。 2.信号 sinc2(100t),|t|≤t0 m(t)= 0, 其它 采用频率调制调制为1000HZ的载波。频偏常数为kf=50,t0=0.2
PLL
- PPL讲义,关于鉴相器方面的技术资料,对于用单片机编程有好处。-PPL notes, phase detector on the technical information, good use of single-chip programming.
dianneng
- 使用labview7.1编写的一个简单的虚拟电能质量检测仪,监测参数包括电压偏差、频率偏差、频域谐波分析、电压波动、三相不平衡度等。-Labview7.1 prepared using a simple detector of virtual power quality, monitoring parameters, including voltage deviation, frequency deviation, frequency-domain harmonic analysis, volt
ADF4157
- ADF4157是ADI公司出品的一款锁相环芯片,它含有一个鉴相器,一个电子泵,一个sigma delta 分频器-ADI Corporation ADF4157 is a production of the chip phase-locked loop, which contains a phase detector, an electronic pump, a sigma delta prescaler
tongxin
- 自己做的测频测相器(硬件使用EPM240采样计数mega16取数和控制),此为EPM240的程序,使用quartus编程,主要包含两个接近20位的计数器。-This is the frequency and phase detector (hardware using EPM240 sampling and counting, mega16 take the number and control), this is EPM240 procedures, using quartus program
avr
- 自己做的测频测相器(硬件使用EPM240采样计数mega16取数和控制),此为Emega16的程序,使用ICCAVR编程,主要包含测频和测相的计数值的处理,和LCD12864的显示-This is frequency and phase detector(hardware using EPM240 sample count mega16 take the number and control), this is Emega16 procedures, the use of ICCAVR prog
cordic_atan
- 用verilog语言实现计算反正切函数,在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程,基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真,并取其中间的I和Q支路做为verilog文件的输入,并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法,其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值,并不需要绝对的值,所以并没有给予加权,需要的同学可以自己加上。-Calculated usin
musicdsp
- musicdsp source code archive-Analysis Beat Detector Class Coefficients for Daubechies wavelets 1-38 DFT Envelope detector Envelope Detector class (C++) Envelope follower with different attack and release Fast in-place Walsh-Hadamard Tra
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上,首先比较码环与载波环不同鉴相器的性能,然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析,最后设计 了合适的码环与载波环路,并用实际采集的GPS 数据论证了所设计环路的有效性,为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the diffe
DPD_Digital-phase-detector
- This the phase difference calculation method based on digital phase detector DPD. It uses Hilbert transform to shift one signal the other by 90 degree. Then by some manipulation, extract the phase difference between two signals.-This the phase diff