5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident

基于Matlab的Coherent 16QAM simulation。包括产生伪随机比特序列、产生电脉冲序列、NRZ调制、AWGN 信道 plot_opti_spec、平衡探测器、均衡等。-Matlab-based Coherent 16QAM simulation. Comprises generating pseudo-random bit sequence, generating an electrical pulse sequence, NRZ modulation, AWGN chan

设计一个11位巴克码序列峰值检测器，巴克码序列为11’b 11100010010。要求 能够检测巴克码序列峰值； 在存在1bits错误情况下，能够检测巴克码序列峰值。 写出测试仿真程序-Design of a 11 Barker code sequence peak detector, Barker code sequence 11 b 11100010010. Claim Barker code sequence can be detected peak 1bits in

根据相机的指向数据，实现对亮星星表9110颗星在探测器上的模拟投影，得到序列星图-According to the data of the camera, to achieve the Bright Star Catalogue 9110 stars on the detector simulation projection to obtain sequence star map

采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, b