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vga_timing_gen
- verilog文件 实现VGA时序驱动，产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.
timing_recovery
- timing recovery carrier program
schmidl
- OFDM同步定时程序，主要是Schmid和lPark定时算法。-OFDM timing synchronization process, the main Schmid and are regularly lPark algorithm.
perfect_timing_II.pdf
- 完美时序 - 时钟产生和分发设计指南,很不错的理解时绪分析。-Perfect Timing
timing_recovery
- 此算法是用于ofdm定时同步的定时恢复的，通过MATLAB的simulink仿真实现-This algorithm is used for OFDM Timing Synchronization Timing Recovery through MATLAB implementation of the simulink simulation
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
lcd_timing_controller
- DE2-70 ltm timing Controller
HDB3encoder
- 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission i
Timing
- Timing system which communicates with a microcontroler based system
qpsksystem_SJSU_mdl
- QPSK modulation system with recover loops-This is a model of a QPSK modulation system for transmission over a bandpass channel with fc = 100 Hz and B = 30 Hz and AWGN at the receiver. SRRC fi lters with excess bandwidth α = 0.18 are employed. Th
ofdmsystem
- ofdm系统仿真，包括定时、频偏和信道估计。参数都可进行灵活设置，是一个少有的实现ofdm全部功能的程序。很值得推荐。-ofdm simulation, include the timing and frequency errors correction and channel estimation, all the parameters can bet set easily.
2
- new symbol timing synchronization method for OFDM based WLANs
marquee
- The TRealTimeMarquee is a horizontal scrolling marquee control, and uses Windows multimedia timer for its timing needs. By this control, the marquee always runs smoothly even if your application is busy by doing some time consuming operations.-The TR
3_3_function
- this file contain the timing recovery of DSSS reciver
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
TimingRecovery_Simulink
- timing recovery on Simulink
VESAMonitorTimingSpecificationv1_0
- This a scan of the VESA Monitor Timing Specification v 1.0. Very usefull doc in all jobs related to PC display interfaces.-This is a scan of the VESA Monitor Timing Specification v 1.0. Very usefull doc in all jobs related to PC display interfaces.
Prashanth_Chandran_thesis
- thesis based on symbol timing recovery based on fpga
timing_recovery_1
- matlab file for symbol timing recovery.