搜索资源列表
VGA Output
- VGA Timing Output display
TimingDesigner
- 非常简单易用的画时序图工具，用于时序设计、流程分析很实用-Very easy to use timing diagram drawing tool for timing design, flow analysis is very useful
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
lcd_timing_controller
- DE2-70 ltm timing Controller
HDB3encoder
- 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission i
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
Prashanth_Chandran_thesis
- thesis based on symbol timing recovery based on fpga
CAMPARE-FOR-TIMING
- 基于MC9S12dg128的CAMPARE FOR TIMING应用示例 精确定时10ms-Based on MC9S12dg128 of CAMPARE FOR TIMING Application Examples precise timing 10ms
RTI-FOR-TIMING
- 基于mc9s12dg128的RTI for Timing应用示例 精确定时10.24ms-Based on the RTI for Timing Applications mc9s12dg128 sample accurate timing 10.24ms
Timing-Reply-ring
- MSP430135单片机定时输出即一些系统初始化设置-Timing output MSP430135 MCU initialization settings that some systems
static_time_analysis
- Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
VESA-timing_dmt(NEW)10
- 介绍VESA标准显示屏监控时序，详细介绍分辨率，行，场频率-This document includes all current VESA Monitor Timing Standards & Guidelines. Guidelines are subjected to the same VESA review and approval process as Standards , but are designated as Guidelines to ease concer
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
1ms-timer-timing-B
- MSP430F149的定时器B产生大约1ms的定时，使主程序退出低功耗模式。主程序执行一遍流程，再次进入休眠，等待下一次被唤醒。中断TIME_FA次后，改变定时器的定时时间。每次中断的时候翻转P4.1脚的电平，使LED熄灭或者点亮。-MSP430F149 generate approximately 1ms timer timing B, the main program to exit low-power mode. Main program execution once the proces
Ward-Calling-System_-timing-_latch
- 病房呼叫系统 锁存器 计时模块 优选模块 时间模块-Ward calling system timing module latch time module selection module
HC11-timing
- hc11 timing source code and simulation in Verilog program
timing-marquee
- 自己在做课程设计的时候做的一个简单的定时跑马灯程序。-A simple timing marquee program.
can-bus-bit-timing-setting
- 在CAN总线中,位定时有一点小错误就会导致总线性能严重下降。虽然在许多情况下，位同步会修补由于位定时设置不当而产生的错误，但不能完全避免出错情况，并且在遇到两个或多个CAN节点同时发送的情况时，错误的采样点会使节点启动错误认可标志，使节点不能赢得总线上的任何活动。因此要分析、解决这样的错误就需要对CAN总线位定时中的位同步和CAN节点的工作过程有一个深入的了解。本文描述了CAN总线位同步的运行规则以及如何对位定时的参数进行设置。-In the CAN bus, there is a little