搜索资源列表
VGA Output
- VGA Timing Output display
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
lcd_timing_controller
- DE2-70 ltm timing Controller
HDB3encoder
- 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission i
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
Prashanth_Chandran_thesis
- thesis based on symbol timing recovery based on fpga
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
Ward-Calling-System_-timing-_latch
- 病房呼叫系统 锁存器 计时模块 优选模块 时间模块-Ward calling system timing module latch time module selection module
HC11-timing
- hc11 timing source code and simulation in Verilog program
VESA-VGA
- VESA VGA时序标准，介绍各种VGA时序。-VESA VGA timing standards, introduce a variety of VGA timing.
time
- 几篇解读FPGA内部时序问题的好文章，从最近本的Tco,Tsu，Th等入门。一直到如何对时序进行约束，如何处理各种影响FPGA时钟的因素。如何读懂时序图（Interpreting the Timing Diagram） -FPGA internal timing problems read several good articles, from the most recent of Tco, Tsu, Th and other entry. How the timing has to be co
timing
- Video RGB timing搭配FPGA系統及三色LED控制,可以實現色序法(Field sequential display).-Video RGB timing with FPGA and three-color LED control system can achieve color sequential (Field sequential display).
timing
- 对输入CPLD/FPGA特定口的前后两个脉冲间隔进行计数并输出-timing for the break of 2 impulses into the certain input of CPLD/FPGA and output
VHDL-test-code-Timing-Components
- VHDL实验代码：时序部件实验-启停电路，这是一个基于VHDL开发的程序，非常的实用-VHDL test code: Timing Components experiment- start-stop circuit, a VHDL-based development process, a very practical
Timing-analysis
- FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention
xilinx-timing-constrains
- ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助-In this file , global timing constraints is introduced very clearly. It can really helps
Zhou-timing-circuit-to-achieve
- 简单方便周计时电路的Verilog程序实现-Zhou timing circuit to achieve
Timing-and-Clocking
- fpga中关于时序与时钟的深度剖析，解释了很多设计时遇到的问题以及解决方案-fpga in depth analysis of the timing clock, explains a lot of the problems encountered in the design and solutions