搜索资源列表
data_check_hand_in
- 一个基于状态机的8位码流检测实现，Verilog语言，在ISE 10.1环境下编译通过。-A state machine-based 8-bit code stream detection to achieve, Verilog language, the ISE 10.1 environment compile.
FSM
- 有限状态机，用Verilog语言，执行正确，仿真通过。-Finite state machine, with the Verilog language, the implementation of the right, simulation pass.
rom_con_aa
- VERILOG 多线程控制程序，实现状态机控制ad采集-VERILOG multi-threaded control program, to achieve a state machine control ad acquisition
statemachine
- RTL级verilog代码 用状态机实现 将输入数据写入16位寄存器，输出其除以7所得的余数（4位）-RTL-lever verilog code Using FSM to realize the following function:input the data into a 16bit register, divide it by 7, and output the 4-bit remainder
traffic_light
- 用Verilog HDL语言写一个交通控制灯的状态机。十字路口，红绿灯，带倒计时功能，也可以自行变换亮灯时间。-Verilog HDL language used to write a traffic control light state machine. Intersections, traffic lights, with the countdown function, you can also change their own light time.
caideng
- 这个程序是用verilog语言编写的彩灯的小程序，使用状态机来实现，可以实现多种花型，有具体的程序！-This program is written in verilog small lantern, the use of state machine, you can achieve a variety of flowers, there are specific procedures!
chuzuche
- 本程序使用verilog语言编写的出租车计价系统，实现时距并计！主要用状态机来实现！-This program uses the taxi meter verilog language system, and taking into account the time-distance! State machine is mainly used to achieve!
yinliao
- 本程序采用verilog语言编写实现仿真自动饮料机的功能，采用状态机来实现！-This procedure uses verilog language automatic beverage machine emulation capabilities, the use of state machine!
state_machine
- 基于FPGA用VHDL编写的状态机控制步进电机.-Prepared by the state machine control VERILOG stepper motor.
STATE_MECHINE
- FPGA 状态机控制步进电机..verilog-FPGA state machine controlled stepper motor .. verilog
ledwatertest
- 一个用verilog 编写的流水灯程序，对于初学者比较有用，主要用于理解状态机转换。-Written in a flowing light with verilog program more useful for beginners, mainly for the understanding of the state machine transition.
verilogshiyansoure37
- verilog实验的基本程序，包括状态机、数码管、流水灯、蜂鸣器、点阵、键盘等等，超详细的程序、适合初学者-verilog basic experimental procedures, including the state machine, digital control, water lights, buzzers, dot matrix, keyboard, etc., super detailed procedures, suitable for beginners
State-machine
- 实现了一个简单状态机的转换功能，用Verilog语言。-State machine implements a simple conversion function, with the Verilog language.
cheweideng
- 用Verilog语言编写的车尾灯，用状态机来实现，3个LED显示左转，3个LED显示右转，6个灯显示刹车-Using Verilog language taillights, the state machine to achieve, three LED display left, three right LED display, six brake light display
how-to-use-state-machine
- 三段式状态机的用法，对于想学习verilog及VHDL编程的人来说是必看的内容-The use of three-state machine, for those who want to learn verilog and VHDL programming is a must-see content people
three_machine_study
- verilog 三段式状态机的写法，很好的Pdf-verilog three-state machine is written, a good Pdf
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
state-machine-design
- Verilog and VHDL状态机设计，内含源代码，希望对大家有所帮助。-Verilog and VHDL state machine design, including source code, we want to help.
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
mealy_sequence
- 实现米粒状态机 用verilog语言实现状态机的过程-Implement a state machine with a grain of rice verilog state machine language course