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risc_cpu
- 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块
RISC_CPU
- RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书
16bit_cpu
- 16位的RISC_CPU， 应该对大家有帮助
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this e
ALU
- 此代码能高速实算术逻辑单元的功能，适合risc_CPU的设计。若有不足，请多多包含。-This code can be really high-speed arithmetic logic unit function, suitable for risc_CPU design. If insufficient, please contain.
risc_cpu
- This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
RISC_CPU
- Verilog HDL编写的一个精简指令的处理器，很好用，可用来学习-Verilog HDL RISC_CPU
RISC_CPU
- Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<
RISC_CPU
- 利用VHDL实现risc cpu，IPcode 的risc cpu-Using VHDL implementation risc cpu, IPcode the risc cpu
RSIC_CPU
- 该模块为简risc_cpu的verig HDL建模-The module is simple risc_cpu of verig HDL Modeling
cpu
- 构造RISC_CPU各个部分的源码，以及验证的pro文件-Construction RISC_CPU various parts of the source code, and verify the pro file
risc
- RISC_CPU 是一个复杂的数字逻辑电路,采用精简指令集,寻址空间位 8K,它的基本部件可分成八个 基本部件 -RISC_CPU is a complex digital logic circuits, using reduced instruction set, addressing space bit 8K, and its basic components can be divided into eight basic components
RISC_cpu
- 基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
RISC_CPU
- 一个简单CPU设计，可以让读者在计算机组成原理和verilog语言方面受益-A simple CPU design, allows the reader to the computer principles and Verilog language benefit
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,
8_RISC_CPU
- risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
RISC_CPU
- 关于risc cpu 的pdf 希望对学习Risc cpu的人有用-Hope that the study of Risc cpu risc cpu pdf
risc_cpu
- RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
8-bit-RISC_CPU
- 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
RISC_CPU
- 这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested o