搜索资源列表
dds_drive.c
- DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号
key_sin
- PS/2键盘加DDS的verilog 设计-PS/2 keyboard plus the verilog design DDS
dds_verilog
- 产生信号发生器的dds的verilog代码，很好的学习资料，值得学习-Verilog code generated signal generator dds good learning materials, it is worth learning
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
DDS_VERILOG
- 超级精简的DDS发生器，用VERILOG编写，请参考-Super-streamlined DDS generator with VERILOG preparation, please refer to
dds_var
- 自己写的一个简单的DDS控制器，此程序包包含完整的VERILOG写的程序，操作有点简单，输出正弦波，方波，锯齿波，通过键盘可以选择输出波形，与大家共享-To write a simple DDS controller, this package contains a complete program written in VERILOG, a bit simple to operate, the output sine wave, square wave, sawtooth, through t
dds_mine
- 这是基于verilog的dds系统设计，比较简单，希望对大家有用-This is based on verilog for dds system design, relatively simple, hope for all of us! ! !
new_128HZ
- 直接数字频率合成器DDS设计，VERILOG实现的，比较好的哦-DDS direct digital frequency synthesizer design, VERILOG implementation, and better oh
DDS_verilog
- 通讯中常用的dds模块的verilog源码打包下载-Communications commonly used in dds module verilog source code package to download
DDS_Timing
- 数字频率合成器DDS，具有和单片机接口的直接数字频率合成器的FPGA实现代码（Verilog）-Digital Frequency Synthesizer
DDSVerilog
- Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
dds_rom
- 此为Verilog编写DDS时，常用模块，为rom模块。-This is the Verilog write DDS, the common module, the module for the rom.
FPGAdds
- 用verilog写的DDS程序，请用QuartusII 8.1以上版本打开-DDS program written using verilog, please QuartusII 8.1 or later to open
DDS_Verilogcode
- 这是一个数字频率综合器（DDS）的Verilog实现源码，采用Quatoues软件综合和仿真-That this is a digital frequency synthesizer (DDS) of the Verilog implementation source code, synthesis and simulation software with Quatoues
DDS_Adder
- DDS加法程序，用verilog程序写成，在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s
design_dds_based_on_verilog
- 基于verilog hdl 的DDS设计-The DDS-based design of verilog hdl
fpga_dds_coylone_2
- dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
DDS_verilog
- 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
DDS_single
- 基于FPGA的单路DDS函数发生器的实现 ，语言为Verilog-FPGA-based single-channel DDS function generator implementation language for Verilog