搜索资源列表
testbench
- 关于如何写Verilog测试台的文档，对于测试程序很有帮助噢-On how to write Verilog test documents, test procedures for helpful Oh
VHDL38decoder
- VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序-38 decoder VHDL language implementation, including program source code file, there are testbench test procedures
vhdltestbench
- testbench,VHDL的，适合初学者使用-testbench
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
Writing_Testbenches_using_System_Verilog
- Testbench creation and development methodology with System Verilog. By Janick Bergeron.
MinWinsockSpi
- verilog ADPLL file with testbench
SPI_FireWall
- verilog spi file with testbench
wince+spi
- verilog vcspi file with testbench
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
adder4
- 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
custom_cordic
- verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set,
spi2-testbench
- test bench for spi communication
vrt
- Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number
generic_testbench
- VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
shiftregister
- Shift Register. VHDL code and its testbench.
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in